CY7C1512AV18-200BZXC Cypress Semiconductor Corp, CY7C1512AV18-200BZXC Datasheet - Page 4

• Manufacturer Part Number: CY7C1512AV18-200BZXC
• Description: IC SRAM 72MBIT 200MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1512AV18-200BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (4M x 18)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Definitions
Document #: 001-06984 Rev. *E
D
WPS
BWS
BWS
BWS
BWS
A
Q
RPS
C
C
K
K
CQ
CQ
ZQ
Pin Name
[x:0]
[x:0]
0
1
2
3
,
,
,
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input Clock
Input Clock
Input Clock
Input Clock
Echo Clock
Echo Clock
Output-
Input-
Input-
Input-
Input-
Input-
Input
I/O
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1512AV18 − D
CY7C1514AV18 − D
Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D
Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1512AV18 − BWS
CY7C1514AV18 − BWS
D
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
Address Inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks during
active read and write operations. These address inputs are multiplexed for both read and write operations.
Internally, the device is organized as 4M x 18 (2 arrays each of 2M x 18) for CY7C1512AV18, and 2M x
36 (2 arrays each of 1M x 36) for CY7C1514AV18. Therefore, only 21 address inputs are needed to
access the entire memory array of CY7C1512AV18, and 20 address inputs for CY7C1514AV18. These
inputs are ignored when the appropriate port is deselected.
Data Output Signals. These pins drive out the requested data during a read operation. Valid data is
driven out on the rising edge of the C and C clocks during read operations, or K and K when in single
clock mode. When the read port is deselected, Q
CY7C1512AV18 − Q
CY7C1514AV18 − Q
Read Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tristated following the next rising edge of the
C clock. Each read access consists of a burst of four sequential transfers.
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. Use C and C together to deskew the flight times of various devices on the board back to the
controller. See
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. Use C and C together to deskew the flight times of various devices on the board back to the
controller. See
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
edge of K.
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q
CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in
CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in the
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q
between ZQ and ground. Alternatively, connect this pin directly to V
impedance mode. This pin cannot be connected directly to GND or left unconnected.
[35:27].
Application Example
Application Example
[17:0]
[35:0]
[17:0]
[35:0]
0
0
controls D
controls D
[x:0]
[x:0]
Switching Characteristics
when in single clock mode.
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
Switching Characteristics
[8:0]
when in single clock mode. All accesses are initiated on the rising
[8:0]
on page 7 for further details.
on page 7 for further details.
, BWS
and BWS
Pin Description
1
controls D
[x:0]
1
controls D
are automatically tristated.
on page 20.
[17:9]
on page 20.
, BWS
[17:9].
2
DDQ
controls D
, which enables the minimum
CY7C1512AV18
CY7C1514AV18
[26:18]
and BWS
Page 4 of 24
3
controls
[x:0]
.
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