CY7C027V-25AI Cypress Semiconductor Corp, CY7C027V-25AI Datasheet - Page 6

• Manufacturer Part Number: CY7C027V-25AI
• Description: 3.3V 32KX16 ASYNC DUAL PORT SRAM
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C027V-25AI

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 512K (32K x 16)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
12. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
13. At any given temperature and voltage condition for any given device, t
14. Test conditions used are Load 2.
15. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading
16. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
17. Test conditions used are Load 1.
18. t
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
ABE
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
WDD
DDD
BLA
BHA
BLC
BHC
PS
WB
WH
BDD
READ CYCLE
WRITE CYCLE
BUSY TIMING
Parameter
[12]
[15]
[15]
[12]
[12]
[12]
[18]
I
port, refer to Read Timing with Busy waveform.
[16]
[16]
OI
BDD
[13, 14, 15]
[13, 14, 15]
[13, 14, 15]
[13, 14, 15]
[14 ,15]
[14, 15]
/I
OH
is a calculated parameter and is the greater of t
and 30-pF load capacitance.
[17]
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
Write Cycle Time
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
Description
Over the Operating Range
WDD
–t
PWE
(actual) or t
DDD
[11]
HZCE
–t
SD
6
is less than t
Min.
(actual).
15
15
12
12
12
10
13
3
3
3
0
0
0
0
3
5
0
-15
LZCE
Max.
15
15
10
10
10
15
15
10
30
25
15
15
15
15
15
and t
HZOE
CY7C027V/028V
CY7C037V/038V
Min.
20
20
16
17
16
12
15
is less than t
3
3
3
0
3
5
0
0
0
0
-20
Max.
LZOE
20
20
12
12
12
20
20
12
40
30
20
20
20
16
20
.
SCE
CY7C027V/028V
CY7C037V/038V
time.
Min.
25
25
20
20
22
15
17
3
3
3
0
0
0
0
3
5
0
-25
Max.
25
25
13
15
15
25
25
15
50
35
20
20
20
17
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns