CY7C027-20AC Cypress Semiconductor Corp, CY7C027-20AC Datasheet
CY7C027-20AC
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CY7C027-20AC Summary of contents
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... CY7C027/028 CY7C037/03832K/64K x 16/18 Dual-Port Static RAM Features ■ True dual-ported memory cells which allow simultaneous access of the same memory location ■ 32K x 16 organization (CY7C027) ■ 64K x 16 organization (CY7C028) ■ 32K x 18 organization (CY7C037) ■ 64K x 18 organization (CY7C038) ■ ...
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... Functional Description The CY7C027/028 and CY7C037/038 are low power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory ...
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... CY7C037/038 [1] -12 12 195 55 0.05 CY7C027/028 CY7C037/038 A8R 74 A9R 73 A10R 72 A11R 71 A12R 70 A13R 69 A14R [7] 68 A15R 67 LBR 66 UBR 65 CE0R 64 CE1R 63 SEMR 62 R/WR 61 GND 60 OER 59 GND 58 I/O17R 57 GND 56 I/O16R 55 I/O15R 54 I/O14R 53 I/O13R 52 I/O12R 51 I/O11R CY7C027/028 CY7C037/038 Unit -15 - 190 180 0.05 0.05 mA Page [+] Feedback ...
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... Upper Byte Select (I/O –I/O for x16 devices; I Lower Byte Select (I/O –I/O for x16 devices; I Interrupt Flag Busy Flag Master or Slave Select Power Ground No Connect CY7C027/028 CY7C037/038 ≥ V and –I/O for x18 –I/O for x18 devices –I/O for x18 devices) ...
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... IH Ind. CY7C027/028 CY7C037/038 [9] ...............................................–0.5V to +7.0V Ambient Temperature V CC ° ° 5V ± 10 +70 C ° ° 5V ± 10% – +85 C CY7C027/028 CY7C037/038 -15 -20 Typ Max Min Typ Max 2.4 0.4 0.4 2.2 0.8 0.8 10 –10 10 190 280 180 265 305 290 50 70 ...
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... GND ≤ [13] 1.00 0.90 0.80 0.70 = 1.4V 0.60 0.50 0.40 0.30 0.20 0.10 0. (b) Load Derating Curve CY7C027/028 CY7C037/038 Max Unit 893Ω OUTPUT 347Ω (c) Three-State Delay (Load 2) (Used for & t CKLZ OLZ OHZ including scope and jig) ≤ ...
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... For information on port-to-port delay through RAM cells from writing port to reading port, refer to 20. Test conditions used are Load 1. Document #: 38-06042 Rev. *D [14] CY7C027/028 CY7C037/038 [1] -12 -15 Min Max Min Max time. SCE is less than t and t is less than t . HZCE LZCE HZOE LZOE Figure 11. CY7C027/028 CY7C037/038 Unit -20 Min Max Page [+] Feedback ...
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... SEM Address Access Time SAA Data Retention Mode The CY7C027/028 and CY7C037/038 are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip enable (CE) must be held HIGH during data retention, ...
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... Document #: 38-06042 Rev DATA VALID t ACE t DOE t LZOE t LZCE [23, 25, 26, 27 LZCE t ABE t ACE t LZCE . This waveform cannot be used for semaphore reads access semaphore SEM = CY7C027/028 CY7C037/038 [23 ,24, 25] t OHA [23, 26, 27] t HZCE t HZOE DATA VALID OHA t HZCE t HZCE Page [+] Feedback ...
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... If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state. Document #: 38-06042 Rev [31] t PWE [34] t HZWE SCE LOW CE or SEM and a LOW PWE . CY7C027/028 CY7C037/038 [28, 29, 30, 31] [34] t HZOE LZWE NOTE [28, 29, 30, 34, 35 allow the I/O drivers to turn off and data HZWE SD Page [+] Feedback ...
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... SPS Document #: 38-06042 Rev SAA VALID ADRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE MATCH t SPS MATCH = CE = HIGH CY7C027/028 CY7C037/038 [37] t OHA t ACE DATA VALID OUT t DOE [38, 39, 40] Page [+] Feedback ...
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... Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Figure 12. Write Timing with Busy Input (M/S=LOW) R/W BUSY Note 41 LOW Document #: 38-06042 Rev MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C027/028 CY7C037/038 [41 BHA t BDD t DDD VALID Page [+] Feedback ...
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... BUSY is asserted. PS Document #: 38-06042 Rev. *D ADDRESS MATCH BLC ADDRESS MATCH BLC ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C027/028 CY7C037/038 [42] t BHC t BHC [42] Page [+] Feedback ...
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... R 44 depends on which enable pin (CE INS INR L Document #: 38-06042 Rev. *D Figure 15. Interrupt Timing Diagrams t WC [43 (FFFF for CY7C028/38) [44] t INR t WC [43 (FFFE for CY7C028/38) [44] t INR ) is deasserted first R asserted last. L CY7C027/028 CY7C037/038 t RC READ 7FFF t RC READ 7FFE Page [+] Feedback ...
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... Architecture The CY7C027/028 and CY7C037/038 consist of an array of 32K and 64K words of 16 and 18 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port ...
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... Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C027/028 CY7C037/038 –I/O Operation 8 Deselected: Power Down Deselected: Power Down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only ...
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... Ordering Information 32K x16 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C027-12AC 15 CY7C027-15AC CY7C027-15AXI 20 CY7C027-20AC CY7C027-20AXC 64K x16 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C028-12AC CY7C028-12AXC 15 CY7C028-15AC CY7C028-15AXC CY7C028-15AI CY7C028-15AXI 20 CY7C028-20AC CY7C028-20AI 32K x18 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code ...
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... Package Diagram Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06042 Rev. *D CY7C027/028 CY7C037/038 51-85048-*C Page [+] Feedback ...
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... Document History Page Document Title: CY7C027/028, CY7C037/038 32K/64K x 16/18 Dual-Port Static RAM Document Number: 38-06042 Orig. of Submission Rev. ECN No. Change ** 110190 SZV *A 122292 RBI *B 236765 YDT *C 377454 PCX *D 2623540 VKN/PYRS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...