ATXMEGA64A3-MU Atmel, ATXMEGA64A3-MU Datasheet - Page 38

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ATXMEGA64A3-MU

Manufacturer Part Number
ATXMEGA64A3-MU
Description
8-bit Microcontrollers - MCU 8/16 bit 1.6V-3.6V 64KB + 4KB
Manufacturer
Atmel
Datasheet

Specifications of ATXMEGA64A3-MU

Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
AVR
Data Bus Width
8 bit/16 bit
Maximum Clock Frequency
32 MHz
Program Memory Size
64 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Package / Case
QFN EP
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
8
Data Rom Size
2 KB
Interface Type
I2C, SPI, USART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
50
Number Of Timers
7
Processor Series
ATXMega
Program Memory Type
Flash
Factory Pack Quantity
260
Supply Voltage - Max
3.6 V
Supply Voltage - Min
1.6 V
22. USART
22.1
22.2
8068T–AVR–12/10
Features
Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication module. The USART supports full duplex communication,
and both asynchronous and clocked synchronous operation. The USART can also be set in
Master SPI mode to be used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide
range of standards. The USART is buffered in both direction, enabling continued data transmis-
sion without any delay between frames. There are separate interrupt vectors for receive and
transmit complete, enabling fully interrupt driven communication. Frame error and buffer over-
flow are detected in hardware and indicated with separate status flags. Even or odd parity
generation and parity check can also be enabled.
One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modula-
tion and demodulation for baud rates up to 115.2 kbps.
PORTC, PORTD, and PORTE each has two USARTs, while PORTF has one USART only.
Notation of these peripherals are USARTC0, USARTC1, USARTD0, USARTD1, USARTE0,
USARTE1 and USARTF0, respectively.
Seven Identical USART peripherals
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High-resolution Arithmetic Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
Master SPI mode for SPI communication
IrDA support through the IRCOM module
XMEGA A3
38

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