CY7C1321CV18-167BZC Cypress Semiconductor Corp, CY7C1321CV18-167BZC Datasheet - Page 20

• Manufacturer Part Number: CY7C1321CV18-167BZC
• Description: IC SRAM 18MBIT 167MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1321CV18-167BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 18M (512K x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Power Up Sequence in DDR-II SRAM
DDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
power up, when the DOFF is tied HIGH, the DLL is locked after
1024 cycles of stable clock.
Power Up Sequence
■
■
■
Power Up Waveforms
Document Number: 001-07161 Rev. *B
Apply power and drive DOFF LOW (all other inputs can be
HIGH or LOW)
❐
❐
After the power and clock (K, K) are stable take DOFF HIGH
The additional 1024 cycles of clocks are required for the DLL
to lock.
Apply V
Apply V
V
DD
/
DOFF
V
DD
DDQ
DDQ
before V
K
K
before V
DDQ
REF
or at the same time as V
Unstable Clock
Clock Start (Clock Starts after
V
DD
/
V
REF
DDQ
V
Stable (< +/- 0.1V DC per 50ns )
DD
/
V
DLL Constraints
■
■
■
DDQ
DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
The DLL functions at frequencies down to 120 MHz.
If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 1024 cycles stable clock
to relock to the desired clock frequency.
Fix High (or tied to V DDQ )
> 1024 Stable clock
Stable)
CY7C1317CV18, CY7C1917CV18
CY7C1319CV18, CY7C1321CV18
Start Normal
Operation
KC Var
Page 20 of 31
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