CY7C1321CV18-167BZC Cypress Semiconductor Corp, CY7C1321CV18-167BZC Datasheet - Page 11

• Manufacturer Part Number: CY7C1321CV18-167BZC
• Description: IC SRAM 18MBIT 167MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1321CV18-167BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 18M (512K x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Burst Address Table
(CY7C1319CV18, CY7C1321CV18)
Write Cycle Descriptions
The write cycle description table for CY7C1317CV18 and CY7C1319CV18 follows.
Write Cycle Descriptions
The write cycle description table for CY7C1917CV18 follows.
Note
Document Number: 001-07161 Rev. *B
8. Is based on a write cycle that was initiated in accordance with the
BWS
NWS
BWS
H
H
H
H
different portions of a write cycle, as long as the setup and hold requirements are achieved.
First Address (External)
H
H
L
L
L
L
L
L
0
0
0
/
BWS
NWS
L–H
L–H
H
H
H
H
L
L
L
L
K
–
–
X..X00
X..X01
X..X10
X..X11
1
1
/
L–H
L–H
L–H
L–H
K
–
–
–
–
L–H
L–H
K
–
–
L–H During the data portion of a write sequence :
L–H During the data portion of a write sequence :
L–H No data is written into the devices during this portion of a write operation.
L-H During the data portion of a write sequence :
K
–
–
–
–
During the Data portion of a write sequence, the single byte (D
During the Data portion of a write sequence, the single byte (D
No data is written into the device during this portion of a write operation.
No data is written into the device during this portion of a write operation.
During the data portion of a write sequence :
CY7C1317CV18 − both nibbles (D
CY7C1319CV18 − both bytes (D
CY7C1317CV18 − both nibbles (D
CY7C1319CV18 − both bytes (D
During the data portion of a write sequence :
CY7C1317CV18 − only the lower nibble (D
CY7C1319CV18 − only the lower byte (D
CY7C1317CV18 − only the lower nibble (D
CY7C1319CV18 − only the lower byte (D
During the data portion of a write sequence :
CY7C1317CV18 − only the upper nibble (D
CY7C1319CV18 − only the upper byte (D
CY7C1317CV18 − only the upper nibble (D
CY7C1319CV18 − only the upper byte (D
No data is written into the devices during this portion of a write operation.
Second Address (Internal)
X..X01
X..X10
X..X00
X..X11
Write Cycle Descriptions
[2, 8]
[17:0]
[17:0]
[7:0]
[7:0]
) are written into the device.
) are written into the device.
) are written into the device,
) are written into the device,
Third Address (Internal)
[8:0]
[8:0]
[17:9]
[17:9]
[3:0]
[3:0]
[7:4]
[7:4]
table. NWS
Comments
) is written into the device, D
) is written into the device, D
CY7C1317CV18, CY7C1917CV18
CY7C1319CV18, CY7C1321CV18
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
X..X10
X..X11
X..X00
X..X01
[2, 8]
0
, NWS
1
, BWS
[8:0]
[8:0]
) is written into the device.
) is written into the device.
0
, BWS
1
Fourth Address (Internal)
, BWS
[17:9]
[17:9]
[8:0]
[8:0]
[7:4]
[7:4]
[3:0]
[3:0]
2
, and BWS
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
X..X00
X..X01
X..X10
X..X11
3
can be altered on
Page 11 of 31
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