CY7C036A-15AC Cypress Semiconductor Corp, CY7C036A-15AC Datasheet
CY7C036A-15AC
Specifications of CY7C036A-15AC
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CY7C036A-15AC Summary of contents
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... Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • 16K x 16 organization (CY7C026A) • 16K x 18 organization (CY7C036A) • 0.35-micron CMOS for optimum speed/power [1] • High-speed access: 12 /15/20 ns • Low operating power — Active: I ...
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... Functional Description The CY7C026A and CY7C036A are low-power CMOS 16K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple pro- cessors access the same piece of data. Two ports are provid- ed, permitting independent, asynchronous access for reads and writes to any location in memory ...
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... Maximum Access Time (ns) Typical Operating Current (mA) Typical Standby Current for I (mA) (Both Ports TTL Level) SB1 Typical Standby Current for I (mA) (Both Ports CMOS Level) SB3 Document #: 38-06046 Rev. *A 100-Pin TQFP Top View CY7C036A (16K x 18 CY7C026A CY7C036A -12 12 195 55 0.05 CY7C026A CY7C036A 84 ...
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... Power Ground No Connect DC Input Voltage Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V Latch-Up Current.................................................... >200 mA Operating Range Range Commercial Industrial CY7C026A CY7C036A Description –I/O for x16 devices; I/O –I/O for x18 devices –I/O for x16 devices; I/O –I/O ...
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... Com’l. 115 185 Indust. [7] Test Conditions MHz 5.0V CC (except output enable means no address or control lines change. This applies only to inputs at CMOS level CY7C026A CY7C036A CY7C026A CY7C036A -15 -20 Min. Typ. Max. Min. Typ. Max. 2.4 2.4 0.4 2.2 2.2 0.8 –10 10 – ...
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... Note: 9. Test Conditions pF. Document #: 38-06046 Rev 250 TH OUTPUT (b) Thévenin Equivalent (Load 1) [9] 3.0V GND = 1. Capacitance (pF) (b) Load Derating Curve CY7C026A CY7C036A 5V OUTPUT 1.4V TH (c) Three-State Delay (Load 2) (Used for HZWE including scope and jig) ALL INPUT PULSES 90% 90% 10% 10 ...
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... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 16. For 15 ns industrial parts t Min. is 0.5 ns. HD Document #: 38-06046 Rev. *A [10] CY7C026A CY7C036A [1] -12 -15 Min. Max. Min. Max less than t and t is less than t HZCE LZCE HZOE LZOE CY7C026A CY7C036A -20 Min. Max. Unit time. SCE . Page ...
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... SEM Address Access Time SAA Data Retention Mode The CY7C026A and CY7C036A are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, with- ...
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... To access RAM Document #: 38-06046 Rev. *A [20, 21, 22 [20, 23, 24] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE and This waveform cannot be used for semaphore reads SEM = access semaphore CY7C026A CY7C036A t OHA DATA VALID t HZCE t HZOE DATA VALID OHA t HZCE t HZCE , SEM = Page ...
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... SCE LOW CE or SEM and a LOW UB or LB. PWE . HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse SD , SEM = SEM = CY7C026A CY7C036A [31] t HZOE LZWE NOTE allow the I/O drivers to turn off and PWE HZWE SD ...
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... SPS Document #: 38-06046 Rev. *A [34 SCE t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE [35, 36, 37] MATCH t SPS MATCH = CE = HIGH CY7C026A CY7C036A t t SAA OHA VALID ADRESS t ACE t SOP DATA VALID OUT t DOE READ CYCLE Page ...
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... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 38 LOW Document #: 38-06046 Rev. *A [38 MATCH t PWE t SD VALID MATCH t BLA t PWE CY7C026A CY7C036A BHA t BDD t DDD VALID t WDD Page ...
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... BUSY will be asserted. PS Document #: 38-06046 Rev. *A [39] ADDRESS MATCH BLC ADDRESS MATCH BLC [39 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C026A CY7C036A t BHC t BHC Page ...
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... INT L Notes: 40. t depends on which enable pin ( depends on which enable pin (CE INS INR Document #: 38-06046 Rev WRITE 3FFF [40 [41] t INR t WC WRITE 3FFE [40 [41] [41] t INR ) is deasserted first R asserted last CY7C026A CY7C036A t RC READ 3FFF t RC READ 3FFE Page ...
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... Architecture The CY7C026A and CY7C036A consist of an array of 16K words of 16 and 18 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These con- trol pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port ...
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... Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C026A CY7C036A I/O –I/O Operation 0 8 High Z Deselected: Power-Down High Z Deselected: Power-Down High Z Write to Upper Byte Only Data In Write to Lower Byte Only ...
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... Speed (ns) Ordering Code [1] 12 CY7C036A-12AC 15 CY7C036A-15AC CY7C036A-15AI 20 CY7C036A-20AC Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06046 Rev. *A © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...
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... Document Title: CY7C026A/CY7C036A 16K X 16/18 Dual-Port Static RAM Document Number: 38-06046 Issue REV. ECN NO. Date ** 110198 09/29/01 *A 122296 12/27/02 Document #: 38-06046 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-00832 to 38-06046 RBI Power up requirements added to Maximum Ratings Information CY7C026A ...