M45PE20-VMN6P NUMONYX, M45PE20-VMN6P Datasheet - Page 20

• Manufacturer Part Number: M45PE20-VMN6P
• Description: IC FLASH 2MBIT 75MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE20-VMN6P

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Clock Frequency: 75MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SO
• No. Of Pins: 8
• Base Number: 45
• Frequency: 75MHz
• Ic Generic Number: 45PE20
• Memory Configuration: 256K X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M45PE20
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction
is the only way to put the device in the lowest con-
sumption mode (the Deep Power-down mode). It
can also be used as an extra software protection
mechanism, while the device is not in active use,
since in this mode, the device ignores all Write,
Program and Erase instructions.
Driving Chip Select (S) High deselects the device,
and puts the device in the Standby Power mode (if
there is no internal cycle currently in progress). But
this mode is not the Deep Power-down mode. The
Deep Power-down mode can only be entered by
executing the Deep Power-down (DP) instruction,
to reduce the standby current (from I
as specified in
Once the device has entered the Deep Power-
down mode, all instructions are ignored except the
Release from Deep Power-down (RDP) instruc-
tion. This releases the device from this mode.
Figure 17. Deep Power-down (DP) Instruction Sequence
20/34
S
C
D
Table
11.).
0
1
2
Instruction
3
4
CC1
5
6
to I
7
CC2
,
The Deep Power-down mode automatically stops
at Power-down, and the device always Powers-up
in the Standby Power mode.
The Deep Power-down (DP) instruction is entered
by driving Chip Select (S) Low, followed by the in-
struction code on Serial Data Input (D). Chip Se-
lect (S) must be driven Low for the entire duration
of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the
eighth bit of the instruction code has been latched
in, otherwise the Deep Power-down (DP) instruc-
tion is not executed. As soon as Chip Select (S) is
driven High, it requires a delay of t
supply current is reduced to I
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
jected without having any effects on the cycle that
is in progress.
Stand-by Mode
t
DP
Deep Power-down Mode
CC2
and the Deep
DP
Figure
before the
AI03753D
17..