M45PE20-VMN6P NUMONYX, M45PE20-VMN6P Datasheet - Page 17

• Manufacturer Part Number: M45PE20-VMN6P
• Description: IC FLASH 2MBIT 75MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE20-VMN6P

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Clock Frequency: 75MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SO
• No. Of Pins: 8
• Base Number: 45
• Frequency: 75MHz
• Ic Generic Number: 45PE20
• Memory Configuration: 256K X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Page Program (PP)
The Page Program (PP) instruction allows bytes to
be programmed in the memory (changing bits from
1 to 0, only). Before it can be accepted, a Write En-
able (WREN) instruction must previously have
been executed. After the Write Enable (WREN) in-
struction has been decoded, the device sets the
Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address bytes and at least
one data byte on Serial Data Input (D). If the 8
least significant address bits (A7-A0) are not all
zero, all transmitted data exceeding the ad-
dressed page boundary wrap round, and are pro-
grammed from the start address of the same page
(the one whose 8 least significant address bits
(A7-A0) are all zero). Chip Select (S) must be driv-
en Low for the entire duration of the sequence.
The instruction sequence is shown in
If more than 256 bytes are sent to the device, pre-
viously latched data are discarded and the last 256
data bytes are guaranteed to be programmed cor-
rectly within the same page. If less than 256 Data
bytes are sent to device, they are correctly pro-
grammed at the requested addresses without hav-
ing any effects on the other bytes of the same
page.
Figure 14. Page Program (PP) Instruction Sequence
Note: 1. Address bits A23 to A18 are Don’t Care
2. 1 n 256
S
C
D
S
C
D
MSB
7
40
0
6
41
1
5
42
Data Byte 2
2
Instruction
4
43 44 45 46 47 48 49 50
3
3
4
2
5
1
Figure
6
0
MSB
7
7
MSB
23
14..
8
6
22 21
9 10
5
Data Byte 3
24-Bit Address
4
51
3
For optimized timings, it is recommended to use
the Page Program (PP) instruction to program all
consecutive targeted Bytes in a single sequence
versus using several Page Program (PP) se-
quences with each containing only a few Bytes
(see
Chip Select (S) must be driven High after the
eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not
executed.
As soon as Chip Select (S) is driven High, the self-
timed Page Program cycle (whose duration is t
is initiated. While the Page Program cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is complete, the Write Enable Latch (WEL)
bit is reset.
A Page Program (PP) instruction applied to a page
that is Hardware Protected is not executed.
Any Page Program (PP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
jected without having any effects on the cycle that
is in progress.
52 53 54 55
3
28 29 30 31 32 33 34 35
2
2
AC Characteristics (33MHz
1
1
0
0
MSB
7
MSB
7
6
6
5
Data Byte 1
5
Data Byte n
4
4
3
36 37 38
3
2
2
1
1
0
39
operation)).
0
AI04044
M45PE20
17/34
PP
)