IS61LPS51236A-200TQLI ISSI, Integrated Silicon Solution Inc, IS61LPS51236A-200TQLI Datasheet - Page 12

• Manufacturer Part Number: IS61LPS51236A-200TQLI
• Description: IC SRAM 18MBIT 200MHZ 100TQFP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61LPS51236A-200TQLI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Density: 18Mb
• Access Time (max): 3.1ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 475mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1100; IS61LPS51236A-200TQLI

IS61VPS25672A, IS61LPS25672A
IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A
TRUTH TABLE
NOTE:
12
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
NEXT CYCLE
Deselected
Read, Begin Burst
Read, Begin Burst
Write, Begin Burst
Read, Begin Burst
Read, Begin Burst
Read, Continue Burst
Read, Continue Burst
Read, Continue Burst
Read, Continue Burst
Write, Continue Burst
Write, Continue Burst
Read, Suspend Burst
Read, Suspend Burst
Read, Suspend Burst
Read, Suspend Burst
Write, Suspend Burst
Write, Suspend Burst
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
BWx, BWE, GW HIGH.
DQPc. BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s
and DQPf. BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are avail-
able on the x72 version. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
input data hold time.
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
(1-8)
(1CE option)
GW
GW
GW
GW
GW
H
H
H
H
L
BWE
BWE
BWE
BWE
BWE
H
X
L
L
L
ADDRESS CE
External
External
External
External
External
Current
Current
Current
Current
Current
Current
None
BWa
BWa
Next
Next
Next
Next
Next
Next
BWa
BWa
BWa
X
H
X
L
L
BWb
BWb
BWb
BWb
BWb
CE
CE
CE
CE
H
X
X
H
H
X
H
X
X
H
H
X
H
L
L
L
L
L
X
H
H
X
L
ADSP
ADSP
ADSP
ADSP
ADSP
BWc
BWc
BWc
BWc
BWc
X
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
X
H
H
X
L
L
L
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADSC
ADSC
ADSC
ADSC
ADSC
BWd
BWd
BWd
BWd
BWd
X
X
H
H
H
H
H
H
H
H
H
H
H
H
X
H
H
X
L
L
L
L
L
BWe
BWe
BWe
BWe
BWe
ADV
ADV
ADV
ADV
ADV
X
X
X
X
X
X
H
H
H
H
H
H
X
H
H
X
L
L
L
L
L
L
L
WRITE
WRITE
WRITE
WRITE
WRITE
BWf
BWf
BWf
BWf
BWf
X
X
X
H
H
H
H
H
H
H
H
H
H
X
H
H
X
L
L
L
L
L
L
BWg
BWg
BWg
BWg
BWg
OE
OE
OE
OE
OE
X
H
X
H
H
H
X
X
H
H
X
X
X
H
H
X
L
L
L
L
L
L
L
BWh
BWh
BWh
BWh
BWh
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
H
H
X
L
DQ
02/12/2010
Q
Q
Q
Q
Q
Q
D
D
D
D
D
Rev. N