SST49LF080A-33-4C-WHE Microchip Technology, SST49LF080A-33-4C-WHE Datasheet - Page 25
![IC FLASH SER LPC 8MBIT 32TSOP](/photos/16/11/161161/sst49lf080a_sml.jpg)
SST49LF080A-33-4C-WHE
Manufacturer Part Number
SST49LF080A-33-4C-WHE
Description
IC FLASH SER LPC 8MBIT 32TSOP
Manufacturer
Microchip Technology
Datasheets
1.SST49LF080A-33-4C-NHE.pdf
(49 pages)
2.SST49LF080A-33-4C-NHE.pdf
(2 pages)
3.SST49LF080A-33-4C-NHE.pdf
(2 pages)
Specifications of SST49LF080A-33-4C-WHE
Memory Type
FLASH
Memory Size
8M (1M x 8)
Operating Temperature
0°C ~ 85°C
Package / Case
32-TSOP
Format - Memory
FLASH
Speed
33MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Data Bus Width
8 bit
Architecture
Sectored
Interface Type
Parallel, Serial
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
12 mA
Mounting Style
SMD/SMT
Organization
4 KB x 256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SST49LF080A-33-4C-WHE
Manufacturer:
SST
Quantity:
1 815
Part Number:
SST49LF080A-33-4C-WHE
Manufacturer:
SST
Quantity:
20 000
8 Mbit LPC Flash
SST49LF080A
©2006 Silicon Storage Technology, Inc.
FIGURE 11: Block-Erase Command Sequence (LPC Mode)
LFRAME#
LFRAME#
LFRAME#
LFRAME#
LFRAME#
LFRAME#
LAD[3:0]
LAD[3:0]
LAD[3:0]
LAD[3:0]
LAD[3:0]
LAD[3:0]
LCLK
LCLK
LCLK
LCLK
LCLK
LCLK
CE#
CE#
CE#
CE#
CE#
CE#
Note: 1. Address must be within memory address range specified in Table 4.
Write the 6th command (target sector to be erased) to the device in LPC mode.
BA X = Block Address
6th Start
1st Start
4th Start
3rd Start
1 Clock 1 Clock
1 Clock 1 Clock
2nd Start
1 Clock 1 Clock
1 Clock 1 Clock
5th
0000b
0000b
1 Clock 1 Clock
0000b 011Xb
0000b
0000b
1 Clock 1 Clock
0000b
Memory
Memory
Memory
Memory
Memory
Cycle
Cycle
011Xb
Cycle
011Xb
Write
Write
Write
Cycle
011Xb
Write
Cycle
011Xb
Memory
Write
Cycle
011Xb
Write
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
Load Address "YYYY 5555H" in 8 Clocks
Load Address "YYYY 2AAAH" in 8 Clocks
Load Address "YYYY 5555H" in 8 Clocks
Load Address "YYYY 5555H" in 8 Clocks
Load Address "YYYY 2AAAH" in 8 Clocks
Load Block Address in 8 Clocks
A[23:20]
A[23:20] A[19:16]
A[23:20] A[19:16]
A[23:20] A[19:16]
A[23:20] A[19:16]
A[23:20] A[19:16]
Write the 1st command to the device in LPC mode.
Write the 4th command to the device in LPC mode.
Write the 5th command to the device in LPC mode.
Address 1
Address 1
A[19:16]
Write the 3rd command to the device in LPC mode.
Address 1
Address 1
Write the 2nd command to the device in LPC mode.
Address 1
Address 1
0101b
0101b
BA X
0010b
0101b
0010b
25
XXXXb XXXXb XXXXb
0101b
0101b
1010b
0101b
1010b
0101b
0101b
1010b
0101b
1010b
1010b
0101b
0101b
0101b
Load Data "AAH" in 2 Clocks
Load Data "AAH" in 2 Clocks
Load Data "55H" in 2 Clocks
Load Data “50” in 2 Clocks
1010b
Load Data "80H" in 2 Clocks
Load Data "55H" in 2 Clocks
1010b
0000b
1010b
0101b
0000b
0101b
Data
Data
Data
Data
Data
Data
0101b
1010b
1010b
0101b
1000b
0101b
1111b
1111b
1111b
1111b
1111b
2 Clocks
2 Clocks
2 Clocks
2 Clocks
1111b
2 Clocks
2 Clocks
TAR
TAR
TAR
TAR
TAR
TAR
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
1 Clock
1 Clock
1 Clock
1 Clock
Sync
0000b
Sync
0000b
1 Clock
Sync
0000b
Sync
0000b
0000b
1 Clock
Sync
Sync
0000b
TAR
TAR
TAR
TAR
TAR
TAR
S71235-02-000
erase start
Command
erase start
Command
Start next
Start next
Command
Command
Command
Start next
Start next
Internal
Internal
Start next
1 Clock
1 Clock
1 Clock
1235 F10.0
1 Clock
1 Clock
Data Sheet
5/06