SST49LF080A-33-4C-WHE Microchip Technology, SST49LF080A-33-4C-WHE Datasheet - Page 17

• Manufacturer Part Number: SST49LF080A-33-4C-WHE
• Description: IC FLASH SER LPC 8MBIT 32TSOP
• Manufacturer: Microchip Technology

Specifications of SST49LF080A-33-4C-WHE

• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 32-TSOP
• Format - Memory: FLASH
• Speed: 33MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Data Bus Width: 8 bit
• Architecture: Sectored
• Interface Type: Parallel, Serial
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 12 mA
• Mounting Style: SMD/SMT
• Organization: 4 KB x 256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

8 Mbit LPC Flash
SST49LF080A
PARALLEL PROGRAMMING MODE
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. The data portion of the software com-
mand sequence is latched on the rising edge of WE#.
During the software command sequence the row address
is latched on the falling edge of R/C# and the column
address is latched on the rising edge of R/C#.
Reset
Driving the RST# low will initiate a hardware reset of the
SST49LF080A. See Table 23 for Reset timing parameters
and Figure 17 for Reset timing diagram.
Read
The Read operation of the SST49LF080A device is con-
trolled by OE#. OE# is the output control and is used to
gate data from the output pins. Refer to the Read cycle tim-
ing diagram, Figure 18, for further details.
Byte-Program Operation
The SST49LF080A device is programmed on a byte-by-
byte basis. Before programming, one must ensure that the
sector in which the byte is programmed is fully erased. The
Byte-Program operation is initiated by executing a four-byte
command load sequence for Software Data Protection with
address (BA) and data in the last byte sequence. During
the Byte-Program operation, the row address (A
latched on the falling edge of R/C# and the column address
(A
bus is latched on the rising edge of WE#. The Program
operation, once initiated, will be completed, within 20 µs.
See Figure 22 for Program operation timing diagram and
Figure 34 for its flowchart. During the Program operation,
the only valid reads are Data# Polling and Toggle Bit. Dur-
ing the internal Program operation, the host is free to per-
form additional tasks. Any commands written during the
internal Program operation will be ignored.
©2006 Silicon Storage Technology, Inc.
21
-A
11
) is latched on the rising edge of R/C#. The data
10
-A
0
) is
17
Sector-Erase Operation
The Sector-Erase operation allows the system to erase
the device on a sector-by-sector basis. The sector archi-
tecture is based on uniform sector size of 4 KByte. The
Sector-Erase operation is initiated by executing a six-byte
command load sequence for Software Data Protection
with Sector-Erase command (30H) and sector address
(SA) in the last bus cycle. The internal Erase operation
begins after the sixth WE# pulse. The End-of-Erase can
be determined using either Data# Polling or Toggle Bit
methods. See Figure 23 for Sector-Erase timing wave-
forms. Any commands written during the Sector-Erase
operation will be ignored.
Block-Erase Operation
The Block-Erase Operation allows the system to erase the
device in 64 KByte uniform block size for the
SST49LF080A. The Block-Erase operation is initiated by
executing a six-byte command load sequence for Software
Data Protection with Block-Erase command (50H) and
block address. The internal Block-Erase operation begins
after the sixth WE# pulse. The End-of-Erase can be deter-
mined using either Data# Polling or Toggle Bit methods.
See Figure 24 for Block-Erase timing waveforms. Any com-
mands written during the Block-Erase operation will be
ignored.
Chip-Erase Operation
The SST49LF080A devices provide a Chip-Erase opera-
tion, which allows the user to erase the entire memory
array to the “1s” state. This is useful when the entire device
must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 5555H in the last
byte sequence. The internal Erase operation begins with
the rising edge of the sixth WE#. During the internal Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 11 for the command sequence, Figure 25 for
Chip-Erase timing diagram, and Figure 37 for the flowchart.
Any commands written during the Chip-Erase operation
will be ignored.
S71235-02-000
Data Sheet
5/06