CAT93C66LI-G ON Semiconductor, CAT93C66LI-G Datasheet - Page 8

• Manufacturer Part Number: CAT93C66LI-G
• Description: IC EEPROM 4KBIT 2MHZ 8DIP
• Manufacturer: ON Semiconductor

Specifications of CAT93C66LI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8 or 256 x 16)
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Organization: 512 K x 8 or 256 K x 16
• Interface Type: Microwire
• Maximum Clock Frequency: 1 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 93C66LI-G

Erase All
(Chip Select) pin must be deselected for a minimum of
t
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C66 can be determined by selecting the device and
polling the DO pin. Once cleared, the contents of all memory
bits return to a logical “1” state.
CSMIN
Upon receiving an ERAL command (Figure 7), the CS
DO
CS
SK
DI
DO
CS
SK
DI
. The falling edge of CS will start the self clocking
1
1
0
0
HIGH−Z
0
0
0
1
1
0
Figure 8. WRAL Instruction Timing
Figure 7. ERAL Instruction Timing
http://onsemi.com
8
Write All
(Chip Select) pin must be deselected for a minimum of
t
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy status of
the CAT93C66 can be determined by selecting the device
and polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
CSMIN
D
Upon receiving a WRAL command and data, the CS
N
(Figure 8). The falling edge of CS will start the self
t
SV
D
t
EW
0
STATUS VERIFY
t
CS
BUSY
t
SV
t
EW
READY
STATUS VERIFY
BUSY
t
CSMIN
t
READY
HZ
STANDBY
HIGH−Z
STANDBY
HIGH−Z
t
HZ