CAT93C66LI-G ON Semiconductor, CAT93C66LI-G Datasheet - Page 5

• Manufacturer Part Number: CAT93C66LI-G
• Description: IC EEPROM 4KBIT 2MHZ 8DIP
• Manufacturer: ON Semiconductor

Specifications of CAT93C66LI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8 or 256 x 16)
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Organization: 512 K x 8 or 256 K x 16
• Interface Type: Microwire
• Maximum Clock Frequency: 1 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 93C66LI-G

Device Operation
intended for use with industry standard microprocessors.
The CAT93C66 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 11−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
12−bit instructions control the reading, writing and erase
operations of the device. The CAT93C66 operates on a
single power supply and will generate on chip, the high
voltage required during any write operation.
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation. The serial communication protocol
follows the timing shown in Figure 2.
Table 8. A.C. TEST CONDITIONS
Table 9. INSTRUCTION SET
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
The CAT93C66 is a 4096−bit nonvolatile memory
Instructions, addresses, and write data are clocked into the
Instruction
ERASE
WRITE
EWEN
EWDS
WRAL
READ
ERAL
Start Bit
1
1
1
1
1
1
1
Opcode
10
11
01
00
00
00
00
≤ 50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
0.2 V
0.5 V
Current Source I
CC
CC
11XXXXXXX
00XXXXXXX
10XXXXXXX
01XXXXXXX
to 0.7 V
A8−A0
A8−A0
A8−A0
x8
CC
OLmax
http://onsemi.com
Address
/I
OHmax
4.5 V ≤ V
4.5 V ≤ V
1.8 V ≤ V
1.8 V ≤ V
11XXXXXX
00XXXXXX
10XXXXXX
01XXXXXX
5
A7−A0
A7−A0
A7−A0
; CL = 100 pF
x16
internal write cycle by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
logical “1” start bit, a 2−bit (or 4−bit) opcode, 8−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
The instruction format is shown in Instruction Set table.
The ready/busy status can be determined after the start of
The format for all instructions sent to the device is a
CC
CC
CC
CC
≤ 5.5 V
≤ 5.5 V
≤ 4.5 V
≤ 4.5 V
D7−D0
D7−D0
x8
Data
D15−D0
D15−D0
x16
Read Address AN – A0
Clear Address AN – A0
Write Address AN – A0
Write Enable
Write Disable
Clear All Addresses
Write All Addresses
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