CAT93C66LI-G ON Semiconductor, CAT93C66LI-G Datasheet - Page 7

• Manufacturer Part Number: CAT93C66LI-G
• Description: IC EEPROM 4KBIT 2MHZ 8DIP
• Manufacturer: ON Semiconductor

Specifications of CAT93C66LI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8 or 256 x 16)
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Organization: 512 K x 8 or 256 K x 16
• Interface Type: Microwire
• Maximum Clock Frequency: 1 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 93C66LI-G

Write
and the data, the CS (Chip Select) pin must be deselected for
a minimum of t
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the SK
pin is not necessary after the device has entered the self
clocking mode. The ready/busy status of the CAT93C66 can
be determined by selecting the device and polling the DO
pin. Since this device features Auto−Clear before write, it is
NOT necessary to erase a memory location before it is
written into.
After receiving a WRITE command (Figure 5), address
DO
SK
CS
DI
DO
CS
SK
DI
SK
CS
DI
* ENABLE = 11
CSMIN
DISABLE = 00
. The falling edge of CS will start the
1
1
1
0
1
0
1
1
0
A
N
A
Figure 4. EWEN/EWDS Instruction Timing
N
A
*
N−1
Figure 6. Erase Instruction Timing
Figure 5. Write Instruction Timing
A
N−1
HIGH−Z
HIGH−Z
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A
0
D
7
A
N
0
Erase
(Chip Select) pin must be deasserted for a minimum of
t
clocking clear cycle of the selected memory location. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C66 can be determined by selecting the device and
polling the DO pin. Once cleared, the content of a cleared
location returns to a logical “1” state.
CSMIN
Upon receiving an ERASE command and address, the CS
t
CS
D
(Figure 6). The falling edge of CS will start the self
0
t
SV
t
EW
t
t
EW
CSMIN
BUSY
STATUS
VERIFY
STATUS
VERIFY
STANDBY
t
SV
BUSY
READY
READY
HIGH−Z
STANDBY
STANDBY
t
HIGH−Z
HZ
t
HZ