CY7C1515JV18-167BZI Cypress Semiconductor Corp, CY7C1515JV18-167BZI Datasheet - Page 8

• Manufacturer Part Number: CY7C1515JV18-167BZI
• Description: IC SRAM 72MBIT 167MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1515JV18-167BZI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Application Example
Figure 1
Truth Table
The truth table for CY7C1513JV18, and CY7C1515JV18 follows.
Notes
Document Number: 001-12560 Rev. *F
Write Cycle:
Load address on the rising
edge of K; input write data
on two consecutive K and
K rising edges.
Read Cycle:
Load address on the rising
edge of K; wait one and a
half cycle; read data on
two consecutive C and C
rising edges.
NOP: No Operation
Standby: Clock Stopped
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
3. Device powers up deselected with the outputs in a tristate condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
MASTER
symmetrically.
second read or write request.
ASIC)
(CPU
BUS
or
Operation
shows four QDR II used in an application.
CLKIN/CLKIN#
Delayed K#
DATA OUT
Delayed K
Source K#
Source K
Address
DATA IN
BWS#
WPS#
RPS#
Vt
R
R
Stopped
L-H
L-H
L-H
K
R = 50ohms
D
A
RPS WPS
H
L
H
X
[9]
[8]
↑
L
represents rising edge.
R
P
S
#
Vt = Vddq/2
X
H
X
[9]
W
P
S
#
SRAM #1
Figure 1. Application Example
W
B
S
#
D(A) at K(t + 1)↑ D(A + 1) at K(t + 1)↑ D(A + 2) at K(t + 2)↑ D(A + 3) at K(t + 2)↑
Q(A) at C(t + 1)↑ Q(A + 1) at C(t + 2)↑ Q(A + 2) at C(t + 2)↑ Q(A + 3) at C(t + 3)↑
D = X
Q = High-Z
Previous State
C C#
DQ
CQ/CQ#
K
ZQ
K#
Q
[2, 3, 4, 5, 6, 7]
R = 250ohms
D = X
Q = High-Z
Previous State
DQ
D
A
R
D = X
Q = High-Z
Previous State
Vt
Vt
R
P
S
#
W
P
S
#
DQ
W
B
S
#
SRAM #4
CY7C1513JV18
CY7C1515JV18
C C#
CQ/CQ#
D = X
Q = High-Z
Previous State
K
ZQ
K#
Q
R = 250ohms
Page 8 of 24
DQ
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