CY7C1515JV18-167BZI Cypress Semiconductor Corp, CY7C1515JV18-167BZI Datasheet - Page 24

• Manufacturer Part Number: CY7C1515JV18-167BZI
• Description: IC SRAM 72MBIT 167MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1515JV18-167BZI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document History Page
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© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-12560 Rev. *F
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.
Document Title: CY7C1513JV18/CY7C1515JV18, 72-Mbit QDR
Document Number: 001-12560
Rev.
*A
*B
*C
*D
*E
*F
**
ECN No. Submission
1273951
1462588
2189567
2551501
2746930
2755838
808457
08/25/2009
See ECN
See ECN
See ECN
See ECN
08/12/08
07/31/09
Date
cypress.com/sales.
VKN/AESA Converted from preliminary to final
VKN/AESA Minor Change-Moved to the external web
VKN/AESA Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to “–55°C
VKN/AESA Removed x8 and x9 part number details
Change
Orig. of
VKN
VKN
NJY
wireless.cypress.com
memory.cypress.com
clocks.cypress.com
image.cypress.com
psoc.cypress.com
Description of Change
New data sheet
Removed t
Removed 250MHz and 200MHz speed bins
Updated I
Changed DLL minimum operating frequency from 80MHz to 120MHz
Changed t
to +125°C” in the “Maximum Ratings“on page 21, Updated power up sequence
waveform and its description, Added footnote #21 related to I
from 16.2 to 16.3, Changed Θ
Changed JTAG ID [31:29] from 001 to 000, Added 250MHz and 167MHz speed bins
Post to external website
Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are available and modified
the disclaimer for the Ordering information.
DD
CYC
SD
/I
SB
Revised August 24, 2009
footnote
max spec to 8.4ns
specs
®
II SRAM 4-Word Burst Architecture
JC
spec from 2.3 to 2.1,
CY7C1513JV18
CY7C1515JV18
DD
, Changed Θ
Page 24 of 24
JA
spec
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