CY7C1515JV18-167BZI Cypress Semiconductor Corp, CY7C1515JV18-167BZI Datasheet - Page 4

• Manufacturer Part Number: CY7C1515JV18-167BZI
• Description: IC SRAM 72MBIT 167MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1515JV18-167BZI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Definitions
Document Number: 001-12560 Rev. *F
D
WPS
BWS
BWS
BWS
BWS
A
Q
RPS
C
C
K
K
CQ
CQ
ZQ
Pin Name
[x:0]
[x:0]
0
1
2
3
,
,
,
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input Clock
Input Clock
Input Clock
Input Clock
Echo Clock
Echo Clock
Outputs-
Input-
Input-
Input-
Input-
Input-
Input
I/O
Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
CY7C1513JV18 − D
CY7C1515JV18 − D
Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D
Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks when
write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1513JV18 − BWS
CY7C1515JV18 − BWS
BWS
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device .
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
address inputs are multiplexed for both read and write operations. Internally, the device is organized as
4M x 18 (4 arrays each of 1M x 18) for CY7C1513JV18 and 2M x 36 (4 arrays each of 512K x 36) for
CY7C1515JV18. Therefore, only 20 address inputs are needed to access the entire memory array of
CY7C1513JV18 and 19 address inputs for CY7C1515JV18. These inputs are ignored when the appro-
priate port is deselected.
Data Output Signals. These pins drive out the requested data when the read operation is active. Valid
data is driven out on the rising edge of the C and C clocks during read operations, or K and K when in
single clock mode. On deselecting the read port, Q
CY7C1513JV18 − Q
CY7C1515JV18 − Q
Read Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tristated following the next rising edge of the
C clock. Each read access consists of a burst of four sequential transfers.
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
edge of K.
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q
CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks are shown in the
CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks are shown in the
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q
between ZQ and ground. Alternatively, this pin can be connected directly to V
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
2
controls D
[26:18]
[17:0]
[35:0]
[17:0]
[35:0]
Application Example
Application Example
and BWS
0
0
controls D
controls D
[x:0]
[x:0]
when in single clock mode.
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
3
controls D
when in single clock mode. All accesses are initiated on the rising
[8:0]
[8:0]
Switching Characteristics
Switching Characteristics
, BWS
and BWS
on page 8 for further details.
on page 8 for further details.
Pin Description
[35:27].
1
controls D
1
[x:0]
controls D
are automatically tristated.
[17:9]
[17:9].
,
on page 20.
on page 20.
DDQ
CY7C1513JV18
CY7C1515JV18
, which enables the
Page 4 of 24
[x:0]
.
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