CY7C0851AV-133AXC Cypress Semiconductor Corp, CY7C0851AV-133AXC Datasheet - Page 7

• Manufacturer Part Number: CY7C0851AV-133AXC
• Description: IC SRAM 2MBIT 133MHZ 176LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0851AV-133AXC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 2M (64K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Master Reset
The FLEx36 family devices undergo a complete reset by taking
its MRST input LOW. The MRST input can switch asynchro-
nously to the clocks. The MRST initializes the internal burst
counters to zero, and the counter mask registers to all ones
(completely unmasked). The MRST also forces the Mailbox
Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags
HIGH. The MRST must be performed on the FLEx36 family
devices after power up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports of CY7C0853AV.
The highest memory location, 3FFFF is the mailbox for the right
port and 3FFFE is the mailbox for the left port. Table 2 shows that
Table 2. Interrupt Operation Example
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port)
Notes
Document #: 38-06070 Rev. *H
Set Right INT
Reset Right INT
Set Left INT
Reset Left INT
4. CE is internal signal. CE = LOW if CE
5. OE is “Don’t Care” for mailbox operation.
6. At least one of B0, B1, B2, or B3 must be LOW.
7. A16x is a NC for CY7C0851AV, therefore the Interrupt Addresses are FFFF and EFFF; A16x and A15x are NC for CY7C0850AV, therefore the Interrupt Addresses
8. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
9. Counter operation and mask register operation is independent of chip enables.
CLK
X
can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge.
are 7FFF and 6FFF.
MRST
Function
H
H
H
H
H
H
H
H
H
L
L
R
Flag
L
Flag
R
Flag
Flag
CNT/MSK
X
H
H
H
H
H
L
L
L
L
R/W
CNTRST
0
H
L
X
X
= LOW and CE
L
X
H
H
H
H
H
H
H
L
L
[1, 4, 5, 6, 7]
CE
L
X
X
L
L
1
ADS
= HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
X
X
H
H
X
H
L
L
L
L
Left Port
CNTEN
A
3FFFE
3FFFF
0L–17L
H
H
H
X
X
L
L
X
L
X
X
X
Master Reset
Counter Reset
Counter Load
Counter Readback
Counter Increment
Counter Hold
Mask Reset
Mask Load
Mask Readback
Reserved
in order to set the INT
address 3FFFF asserts INT
active for a Write to generate an interrupt. A valid Read of the
3FFFF location by the right port resets INT
byte has to be active in order for a Read to reset the interrupt.
When one port Writes to the other port’s mailbox, the INT of the
port that the mailbox belongs to is asserted LOW. The INT is
reset when the owner (port) of the mailbox Reads the contents
of the mailbox. The interrupt flag is set in a flow-thru mode (i.e.,
it follows the clock edge of the writing port). Also, the flag is reset
in a flow-thru mode (i.e., it follows the clock edge of the reading
port).
Each port can read the other port’s mailbox without resetting the
interrupt. And each port can write to its own mailbox without
setting the interrupt. If an application does not require message
passing, INT pins should be left open.
Operation
INT
X
X
H
L
L
R/W
X
H
X
L
CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Reset address counter to all 0s and mask
register to all 1s.
Reset counter unmasked portion to all 0s.
Load counter with external address value
presented on address lines.
Read out counter internal value on address
lines.
Internally increment address counter value.
Constantly hold the address value for
multiple clock cycles.
Reset mask register to all 1s.
Load mask register with value presented on
the address lines.
Read out mask register value on address
lines.
Operation undefined
R
R
[8, 9]
flag, a Write operation by the left port to
CE
X
X
L
L
R
R
LOW. At least one byte has to be
Right Port
Description
A
3FFFE
3FFFF
0R–17R
X
X
R
HIGH. At least one
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INT
H
X
X
L
R
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