CY7C0851AV-133AXC Cypress Semiconductor Corp, CY7C0851AV-133AXC Datasheet

Page 1

... CY7C0850AV CY7C0851AV 167 167 4.0 4.0 225 225 176TQFP 176TQFP 172FBGA 172FBGA • 198 Champion Court • San Jose CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV for details. 4-Mbit 9-Mbit (128K x 36) (256K x 36) CY7C0852AV CY7C0853AV 167 133 4.0 4.7 225 270 176TQFP 172FBGA ...

Page 2

... Document #: 38-06070 Rev. *H I/O I/O Control Control True Dual-Ported RAM Array Address Address Decode Decode TMS Reset MRST TDO TDI JTAG Logic TCK CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV –DQ ...

Page 3

... A16L A14L DQ22L DQ18L N DQ24L DQ20L DQ8L DQ6L P DQ23L DQ21L TDO VSS Note 2. For CY7C0851AV, pins M1 and M14 are NC. For CY7C0850AV, pins K3, K12 M1, and M14 are NC Document #: 38-06070 Rev. *H Figure 1. 172-Ball BGA (Top View DQ13L VDD DQ11L DQ11R VDD DQ14L DQ12L ...

Page 4

... DQ19L VSS VSS DQ19R DQ18L TDI DQ7L DQ2L DQ2R DQ7R DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R VSS DQ4L VDD DQ1L DQ1R VDD CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV DQ13R VSS NC DQ30R DQ32R DQ14R DQ17R DQ29R DQ33R A0R INTR DQ27R DQ31R A1R A17R DQ28R ...

Page 5

... A 11L 36 A 12L 13L 40 A 14L [ 15L [ 16L 43 DQ 24L 44 DQ 20L Document #: 38-06070 Rev. *H CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV DQ 132 34R DQ 131 35R NC 130 A 129 0R A 128 1R A 127 2R A 126 3R V 125 SS V 124 DD A 123 ...

Page 6

... JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally three-stated except when captured data is shifted out of the JTAG TAP. V Ground Inputs Power Inputs. DD Note 3. These pins are not available for CY7C0853AV device. Document #: 38-06070 Rev. *H CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Description . MAX is asserted LOW when the right L Page [+] Feedback ...

Page 7

... OE is “Don’t Care” for mailbox operation least one of B0, B1, B2 must be LOW. 7. A16x for CY7C0851AV, therefore the Interrupt Addresses are FFFF and EFFF; A16x and A15x are NC for CY7C0850AV, therefore the Interrupt Addresses are 7FFF and 6FFF. 8. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW. ...

Page 8

... Notes 10. This section describes the CY7C0852AV, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0851AV has 16 address bits, register lengths of 16 bits, and a maximum address value of FFFF. The CY7C0850AV has 15 address bits, register lengths of 15 bits, and a maximum address value of 7FFF. ...

Page 9

... When the least significant bit of the mask register is “0,” the counter increments by two. This may be used to connect the CY7C0850AV/CY7C0851AV/CY7C0852AV as a 72-bit single port SRAM in which the counter of one port counts even addresses and the counter of the other port counts odd addresses ...

Page 10

... From 17 Mask Register 17 From Mask 17 From Counter Document #: 38-06070 Rev. *H Mask Register Counter/ Address Register Load/Increment Mirror Counter Increment Logic Wrap 17 Bit 0 +1 Wrap 1 Detect CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV [1] Address RAM Decode Array To Readback and Address Decode 17 Wrap To Counter Page [+] Feedback ...

Page 11

... Figure 5. Programmable Counter-Mask Register Operation CNTINT Example: Load Counter-Mask Register = 3F Load Address Counter = 8 Max Address Register Max + 1 Address Register Document #: 38-06070 Rev Masked Address Unmasked Address CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV [1, 12 Mask Register bit Address Counter bit Page [+] Feedback ...

Page 12

... Places the BYR between TDI and TDO. Loads the IDR with the vendor ID code and places the register between TDI and TDO. Places BYR between TDI and TDO. Forces all CY7C0851AV/CY7C0852AV/ CY7C0853AV output drivers to a High-Z state. Controls boundary to 1/0. Places BYR between TDI and TDO. ...

Page 13

... Operating Current SB5 (V = Max mA OUT Outputs Disabled Capacitance [17] Part Number Parameter CY7C0850AV CY7C0851AV, CY7C0852AV C OUT CY7C0853AV OUT Notes 15. The voltage on any input or I/O pin can not exceed the power pin during power up. 16. Pulse width < 20 ns. 17. C also references C . OUT I/O 18 ...

Page 14

... CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV 3. 590 Ω 435 Ω 90% 10% < -133 -100 CY7C0853AV CY7C0853AV Unit Min Max Min Max 133 100 MHz 7 ...

Page 15

... Master Reset to Outputs Inactive RSF t Master Reset to Counter Interrupt Flag RSCNTINT Reset Time Notes 20. This parameter is guaranteed by design, but it is not production tested. 21. Test conditions used are Load 2. Document #: 38-06070 Rev. *H CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV -167 -133 CY7C0850AV CY7C0850AV CY7C0851AV CY7C0851AV CY7C0853AV CY7C0852AV ...

Page 16

... TDIH t TCK Clock LOW to TDO Valid TDOV t TCK Clock LOW to TDO Invalid TDOX Test Clock TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Document #: 38-06070 Rev. *H CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV Description Figure 7. JTAG Switching Waveform TMSS t TMSH t TDIS t ...

Page 17

... ACTIVE [4, 22, 23, 24, 25] Figure 9. Read Cycle t CL2 A A n+1 n+2 t CD2 CKLZ following the next rising edge of the clock. IH with CNT/MSK = V constantly loads the address on the rising edge of the CLK CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV n n+1 n+2 t OHZ t OLZ t OE Page [+] Feedback ...

Page 18

... SA HA DATA IN DATA OUT Notes 26. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851AV/CY7C0852AV device from this data sheet. ADDRESS = ADDRESS . (B1) (B2) 27. ADS = CNTEN= B0 – LOW; MRST = CNTRST = CNT/MSK = HIGH. 28. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. ...

Page 19

... Document #: 38-06070 Rev n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE t SAD t SCN t CD2 n COUNTER HOLD READ WITH COUNTER CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV [25, 28, 30, 31 n+4 n CD2 CD2 Q Q n+4 n+1 READ [30] t HAD t HCN Q n+2 READ WITH COUNTER Page n+3 [+] Feedback ...

Page 20

... OE DATA IN DATA OUT DISABLED Document #: 38-06070 Rev n n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD t CH2 n+1 n+2 t CD2 Q n READ READ CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV [31 n+2 n+3 n n+3 n+4 WRITE WITH COUNTER n n+1 n+2 READ WRITE READ ...

Page 21

... OUT DISABLED Document #: 38-06070 Rev CH2 n n+2 WRITE READ t CH2 n+1 n OHZ n+2 t CD2 Q n READ DISABLED CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV A A n+4 n CD2 Q Q n+3 n+1 READ WRITE READ A A n+3 n+4 Q n+3 WRITE READ READ Page [+] Feedback ...

Page 22

... CH2 CLK t SAD ADS CNTEN t t SCN HCN ADDRESS COUNTER A INTERNAL n ADDRESS OE DATA OUT INCREMENT Document #: 38-06070 Rev HAD A A n+1 Q n+1 NO OPERATION READ READ READBACK INCREMENT CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV n n+2 n+3 n n+3 n+2 READ READ INCREMENT INCREMENT Page [+] Feedback ...

Page 23

... No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset. 34. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. Document #: 38-06070 Rev. *H [32, 33] Figure 19. Counter Reset CD2 t CKLZ WRITE READ READ ADDRESS 0 ADDRESS 1 CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV ...

Page 24

... the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines. Document #: 38-06070 Rev CA2 CM2 n CD2 CKHZ CKLZ Q n INCREMENT in next clock cycle. CKLZ . CKHZ CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV [35, 36, 37, 38 n+4 n n+1 n+2 n+3 Page [+] Feedback ...

Page 25

... Document #: 38-06070 Rev CKLZ n t CCS CD2 CNTRST = MRST = CNT/MSK = HIGH CYC2 CD2 CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV [39, 40, 41 violated, indeterminate data is Read out. CCS + t ) after the rising edge of R_Port's clock CYC2 CD2 ) after the rising edge of R_Port's clock. Page CCS [+] Feedback ...

Page 26

... R/W = CNTRST = MRST = HIGH 43. CNTINT is always driven. 44. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 45. The mask register assumed to have the value of 1FFFFh. Document #: 38-06070 Rev. *H CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV [34, 42, 43, 44, 45] 1FFFE 1FFFF Last_Loaded t ...

Page 27

... When CE changes state, deselection and Read happen after one cycle of latency. Document #: 38-06070 Rev. *H [46, 47, 48, 49 SINT t RINT 3FFFF m+1 m [1, 8, 51, 52] Outputs CE R/W DQ – High High OUT H X High-Z CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV A A n+2 n m+3 m+4 Operation 35 Deselected Deselected Write Read Outputs Disabled Page [+] Feedback ...

Page 28

... CY7C0851AV-167AXC 133 CY7C0851AV-133BBC 51-85114 172-Ball Grid Array ( 1.25 mm) with 1 mm pitch CY7C0851AV-133AC 51-85132 176-Pin Thin Quad Flat Pack ( 1.4 mm) CY7C0851AV-133AXC CY7C0851AV-133BBI 51-85114 172-Ball Grid Array ( 1.25 mm) with 1 mm pitch CY7C0851AV-133AI 51-85132 176-Pin Thin Quad Flat Pack ( 1.4 mm) CY7C0851AV-133AXI 32K × 36 (1M) 3.3V Synchronous CY7C0850AV Dual-Port SRAM ...

Page 29

... Package Diagrams Figure 24. 172-Ball FBGA ( 1.25 mm) (51-85114) Document #: 38-06070 Rev. *H CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV 51-85114-*B Page [+] Feedback ...

Page 30

... Package Diagrams Figure 25. 176-Pin Thin Quad Flat Pack (24 × 24 × 1.4 mm) (51-85132) Document #: 38-06070 Rev. *H CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV 51-85132-** Page [+] Feedback ...

Page 31

... Document History Page Document Title: CY7C0850AV/CY7C0851AV/CY7C0852AV/CY7C0853AV, FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM Document Number: 38-06070 Submis- Orig. of REV. ECN NO. sion Date Change ** 127809 08/04/03 *A 210948 See ECN *B 216190 See ECN YDT/Dcon Corrected Revision of Document. CMS does not reflect this rev change ...

Page 32

... FLEx36 is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. PSoC Solutions psoc.cypress.com General clocks.cypress.com Low Power/Low Voltage Precision Analog LCD Drive image.cypress.com CAN 2.0b USB Revised July 29, 2008 CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb Page [+] Feedback ...