CY7C026AV-25AXI Cypress Semiconductor Corp, CY7C026AV-25AXI Datasheet - Page 6

• Manufacturer Part Number: CY7C026AV-25AXI
• Description: IC SRAM 256KBIT 25NS 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C026AV-25AXI

• Memory Size: 256K (16K x 16)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 25 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 185 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 3.3 V
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Memory Configuration: 16K X 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2097; CY7C026AV-25AXI

3FFF for the CY7C026AV/36AV) is the mailbox for the right port
and the second highest memory location (FFE for the
CY7C024AV/024BV/41AV/1FFE for the CY7C025AV/51AV,
3FFE for the CY7C026AV/36AV) is the mailbox for the left port.
When one port writes to the other port’s mailbox, an interrupt is
generated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy are
summarized in
Busy
The
CY7C0241AV/0251AV/036AV provide on-chip arbitration to resolve
simultaneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within t
other, the busy logic determines which port has access. If t
violated, one port definitely gains permission to the location, but it is
not predictable which port gets that permission. BUSY is asserted
t
Master/Slave
A M/S pin helps to expand the word width by configuring the
device as a master or a slave. The BUSY output of the master is
connected to the BUSY input of the slave. This enables the
device to interface to a master device with no external compo-
nents. Writing to slave devices must be delayed until after the
BUSY input has settled (t
may begin a write cycle during a contention situation. When tied
HIGH, the M/S pin enables the device to be used as a master
and, therefore, the BUSY line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
Document #: 38-06052 Rev. *M
BLA
after an address match or t
CY7C024AV/024BV/025AV/026AV
Table 2
on page 7.
BLC
or t
BLC
BLA
after CE is taken LOW.
). Otherwise, the slave chip
PS
of each
PS
and
is
Semaphore Operation
The
CY7C0241AV/0251AV/036AV provide eight semaphore latches,
which are separate from the dual port memory locations.
Semaphores are used to reserve resources that are shared
between the two ports. The state of the semaphore indicates that
a resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a semaphore
location. The left port then verifies its success in setting the latch
by reading it. After writing to the semaphore, SEM or OE must
be deasserted for t
The semaphore value is available t
edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource.
Otherwise (reads a one), it assumes the right port has control
and continues to poll the semaphore. When the right side has
relinquished control of the semaphore (by writing a one), the left
side succeeds in gaining control of the semaphore. If the left side
no longer requires the semaphore, a one is written to cancel its
request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A
semaphore address. OE and RW are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only IO
written to the left port of an available semaphore, a one appears
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore is set to one
for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port would immediately own the semaphore as soon as the
left port released it.
operations.
When reading a semaphore, all 16 and 18 data lines output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within t
obtained by one of them. But there is no guarantee which side
controls the semaphore.
CY7C024AV/024BV/025AV/026AV
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
SOP
SPS
Table 3
before attempting to read the semaphore.
of each other, the semaphore is definitely
on page 7 shows sample semaphore
SWRD
0
+ t
is used. If a zero is
0–2
DOE
represents the
after the rising
Page 6 of 20
and
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