CY14B101LA-SP25XI Cypress Semiconductor Corp, CY14B101LA-SP25XI Datasheet - Page 4

• Manufacturer Part Number: CY14B101LA-SP25XI
• Description: IC NVSRAM 1MBIT 25NS 48SSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY14B101LA-SP25XI

• Memory Size: 1M (128K x 8)
• Package / Case: *
• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 16 bit
• Organization: 128 K x 8
• Access Time: 25 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Current: 70 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Pinouts
Table 1. Pin Definitions
Document #: 001-42879 Rev. *K
DQ
DQ
Pin Name
A
A
HSB
0
0
0
V
BHE
0
BLE
V
WE
V
CE
OE
NC
– A
– A
– DQ
CAP
– DQ
CC
SS
[8]
16
15
15
7
(continued)
Input/Output
Input/Output Hardware STORE Busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress.
No connect No connect. This pin is not connected to the die.
I/O Type
DQ
DQ
NC
Ground
NC
NC
V
V
NC
supply
supply
Power
Power
CC
Input
Input
Input
Input
Input
Input
SS
1
3
[5]
0
DQ
NC
HSB
OE
NC
DQ
NC
A
2
8
1
2
Address inputs. Used to select one of the 131,072 bytes of the nvSRAM for x8 configuration.
Address inputs. Used to select one of the 65,536 words of the nvSRAM for x16 configuration.
Bidirectional data I/O lines for ×8 configuration. Used as input or output lines depending on operation.
Bidirectional Data I/O Lines for ×16 configuration. Used as input or output lines depending on operation.
Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tristated on deasserting OE HIGH.
Byte High Enable, Active LOW. Controls DQ
Byte Low Enable, Active LOW. Controls DQ
Ground for the device. Must be connected to the ground of the system.
Power supply inputs to the device. 3.0 V +20%, –10%
When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation HSB is driven HIGH for a short time (t
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvol-
atile elements.
(not to scale)
NC
V
A
A
A
48-FBGA
A
A
A
CAP
Top View
3
14
12
0
3
5
9
[4]
(x8)
A
A
A
A
A
A
A
A
4
15
13
10
1
4
7
16
6
DQ
DQ
NC
CE
WE
NC
A
A
5
11
2
6
5
Figure 3. 48-Ball FBGA and 54-Pin TSOP II
NC
DQ
DQ
NC
NC
V
V
NC
CC
6
SS
4
7
[6]
D
G
B
C
E
F
H
A
7
15
- DQ
Description
- DQ
0
.
8
.
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V
V
WE
NC
NC
NC
NC
NC
CE
CC
A
A
A
A
A
A
SS
A
A
A
A
[7]
0
1
2
3
4
0
1
2
3
4
5
6
7
5
6
7
8
9
10
11
13
14
16
17
18
19
25
26
1
2
3
4
5
6
7
8
9
12
15
20
24
27
21
22
23
54 - TSOP II
(
Top View
not to scale)
(x16)
HHHD
) with standard output high
32
50
49
48
47
45
44
43
42
41
40
39
38
37
36
35
34
33
31
30
29
28
54
53
52
51
46
CY14B101NA
CY14B101LA
DQ
NC
HSB
NC
NC
OE
BHE
DQ
DQ
DQ
NC
NC
NC
A
BLE
DQ
DQ
V
A
A
A
V
V
DQ
DQ
A
A
12
11
15
SS
14
13
10
CC
CAP
[5]
15
14
[6]
[4]
13
12
8
11
10
9
Page 4 of 26
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