CY14B101LA-SP25XI Cypress Semiconductor Corp, CY14B101LA-SP25XI Datasheet - Page 12

IC NVSRAM 1MBIT 25NS 48SSOP

CY14B101LA-SP25XI

Manufacturer Part Number
CY14B101LA-SP25XI
Description
IC NVSRAM 1MBIT 25NS 48SSOP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY14B101LA-SP25XI

Memory Size
1M (128K x 8)
Package / Case
*
Format - Memory
RAM
Memory Type
NVSRAM (Non-Volatile SRAM)
Speed
25ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Data Bus Width
16 bit
Organization
128 K x 8
Access Time
25 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Operating Current
70 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY14B101LA-SP25XI
Manufacturer:
ALTERA
0
Part Number:
CY14B101LA-SP25XI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Part Number:
CY14B101LA-SP25XIT
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Notes
Document #: 001-42879 Rev. *K
22. BHE and BLE are applicable for x16 configuration only.
23. WE must be HIGH during SRAM read cycles.
24. HSB must remain HIGH during Read and Write cycles.
25. CE or WE must be > V
26. If WE is low when CE goes low, the outputs remain in the high impedance state.
Data Output
Data Output
Data Input
BHE, BLE
BHE, BLE
Address
Address
CE
OE
WE
CE
I
CC
IH
during address transitions.
High Impedance
Standby
Figure 7. SRAM Read Cycle #2: CE and OE Controlled
Figure 8. SRAM Write Cycle #1: WE Controlled
Previous Data
t
SA
t
PU
t
LZCE
t
LZOE
t
LZBE
t
Address Valid
t
AA
AW
t
ACE
t
t
HZWE
BW
Address Valid
t
SCE
t
t
t
PWE
DOE
DBE
t
RC
Active
t
WC
t
High Impedance
SD
Input Data Valid
Output Data Valid
t
LZWE
t
HD
[22, 24, 25, 26]
t
HA
[22, 23, 24]
t
t
t
HZBE
HZCE
HZOE
t
PD
CY14B101NA
CY14B101LA
Page 12 of 26
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