CY14B101LA-SP45XI Cypress Semiconductor Corp, CY14B101LA-SP45XI Datasheet - Page 6

• Manufacturer Part Number: CY14B101LA-SP45XI
• Description: IC NVSRAM 1MBIT 45NS 48SSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of CY14B101LA-SP45XI

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 1M (128K x 8)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Word Size: 8b
• Organization: 128Kx8
• Density: 1Mb
• Interface Type: Parallel
• Access Time (max): 45ns
• Package Type: SSOP
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: -40C to 85C
• Pin Count: 48
• Mounting: Surface Mount
• Supply Current: 52mA
• Memory Configuration: 128K X 8
• Access Time: 45ns
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (t
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B101LA/CY14B101NA. But any SRAM read
and write cycles are inhibited until HSB is returned HIGH by MPU
or other external source.
During any STORE operation, regardless of how it is initiated,
the CY14B101LA/CY14B101NA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the nvSRAM memory
access is inhibited for t
Leave the HSB unconnected if it is not used.
Hardware RECALL (Power-up)
During
(V
V
is automatically initiated and takes t
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B101LA/CY14B101NA
Software STORE cycle is initiated by executing sequential CE or
OE controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
Table 2. Mode Selection
Document #: 001-42879 Rev. *K
Notes
10. BHE and BLE are applicable for x16 configuration only.
11. While there are 17 address lines on the CY14B101LA (16 address lines on the CY14B101NA), only the 13 address lines (A
12. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
CC
CC
Rest of the address lines are do not care.
< V
again exceeds the V
CE
H
L
L
L
SWITCH
power-up
), an internal RECALL request is latched. When
or
WE
LZHSB
X
H
H
L
SWITCH
after
time after HSB pin returns HIGH.
any
on powerup, a RECALL cycle
HRECALL
DELAY
OE
low
X
X
L
L
) to complete before
to complete. During
power
BHE, BLE
condition
X
X
L
L
[10]
A
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the t
activated again for the read and write operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed:
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the t
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
15
0xB1C7
0x7C1F
0x4E38
0x83E0
0x703F
0x8B45
- A
X
X
X
0
[11]
Not selected
Read SRAM
Write SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Mode
STORE
RECALL
cycle time is fulfilled, the SRAM is
14
Output high-Z
cycle time, the SRAM is again
- A
Output data
Output data
Output data
Output data
Output data
Output data
Output data
Input data
2
) are used to control software modes.
I/O
CY14B101NA
CY14B101LA
Active
Page 6 of 26
Standby
Power
Active
Active
[12]
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