CY7C024AV-25AXC Cypress Semiconductor Corp, CY7C024AV-25AXC Datasheet - Page 9

• Manufacturer Part Number: CY7C024AV-25AXC
• Description: IC SRAM 64KBIT 25NS 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C024AV-25AXC

• Memory Size: 64K (4K x 16)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 25 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 165 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 3.3 V
• Memory Configuration: 4K X 16
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1790; CY7C024AV-25AXC

Switching Characteristics
Over the Operating Range
Document #: 38-06052 Rev. *M
OUTPUT
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
ABE
WC
SCE
AW
HA
SA
20. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I
21. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
22. At any given temperature and voltage condition for any given device, t
23. Test conditions used are Load 3.
24. This parameter is guaranteed but not tested. For information on port to port delay through RAM cells from writing port to reading port, refer to
Read Cycle
Write Cycle
C = 30 pF
(a) Normal Load (Load 1)
[24]
[24]
[21]
and 30 pF load capacitance.
[21]
[21]
[21]
Parameter
[22, 23, 24]
[22, 23, 24]
[22, 23, 24]
[22, 23, 24]
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Down
Byte Enable Access Time
Write Cycle Time
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Setup to Write Start
3.3V
R1 = 590
R2 = 435
[20]
GND
3.0V
Description

Figure 4. AC Test Loads and Waveforms
OUTPUT
3 ns
(b) Thévenin Equivalent (Load 1)
10%
C = 30pF
ALL INPUT PULSES
90%
HZCE
R
TH
is less than t
= 250
LZCE
90%
and t
V
CY7C024AV/024BV/025AV/026AV
TH
10%
Min
HZOE
20
20
15
15
= 1.4V
3
3
3
0
0
0

CY7C024AV/024BV/025AV/026AV
3 ns
is less than t
CY7C0241AV/0251AV/036AV
CY7C0241AV/0251AV/036AV
-20
OUTPUT
Max
20
20
12
12
12
20
20
(Used for t
(c) Three-State Delay (Load 2)
LZOE
C = 5 pF
including scope and jig)
.
LZ
Min
25
25
20
20
3
3
3
0
0
0
, t
SCE
HZ
, t
-25
time.
HZWE
3.3V
Max
25
25
13
15
15
25
25
Figure
R1 = 590
R2 = 435
, and t
Page 9 of 20
12.
LZWE
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OI
/I
OH
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