CY7C1360C-200AXC Cypress Semiconductor Corp, CY7C1360C-200AXC Datasheet - Page 10

• Manufacturer Part Number: CY7C1360C-200AXC
• Description: IC SRAM 9MBIT 200MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1360C-200AXC

• Memory Size: 9M (256K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3 ns
• Maximum Clock Frequency: 200 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 220 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2126; CY7C1360C-200AXC

Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) CE
appropriate combination of the write inputs (GW, BWE, and
BW
byte(s). ADSC-triggered write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a byte write is conducted, only the selected bytes
are written. Bytes not selected during a byte write operation
remains unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Because the CY7C1360C/CY7C1362C is a common I/O device,
the output enable (OE) must be deasserted HIGH before
presenting data to the DQs inputs. Doing so tristates the output
drivers. As a safety precaution, DQs are automatically tristated
whenever a write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1360C/CY7C1362C provides a two-bit wraparound
counter, fed by A
linear burst sequence. The interleaved burst sequence is
designed specifically to support Intel Pentium applications. The
linear burst sequence is designed to support processors that
follow a linear burst sequence. The burst sequence is user
selectable through the MODE input.
Table 3. ZZ Mode Electrical Characteristics
Document Number: 38-05540 Rev. *K
I
t
t
t
t
Note
DDZZ
ZZS
ZZREC
ZZI
RZZI
5. CE
Parameter
X
) are asserted active to conduct a write to the desired
3
is for A version of TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable.
1
, CE
1
, A
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ inactive to exit sleep current
2
, CE
0
, that implements either an interleaved or
3
[5]
are all asserted active, and (4) the
Description
ZZ > V
ZZ > V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation ‘sleep’ mode. Two clock
cycles are required to enter into or exit from this ‘sleep’ mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the ‘sleep’ mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the ‘sleep’ mode. CE
CE
of t
Table 1. Interleaved Burst Address Table
(MODE = Floating or V
Table 2. Linear Burst Address Table (MODE = GND)
Test Conditions
DD
DD
3
ZZREC
Address
Address
[5]
A
A
– 0.2 V
– 0.2 V
First
First
1
1
, ADSP, and ADSC must remain inactive for the duration
00
01
10
00
11
, A
, A
after the ZZ input returns LOW.
0
0
Address
Address
Second
Second
A
A
1
1
CY7C1360C, CY7C1362C
01
00
11
10
01
, A
, A
DD
0
0
)
2t
Min.
CYC
–
–
–
0
Address
Address
A
A
Third
Third
1
1
10
00
01
10
11
, A
, A
2t
2t
Max.
0
0
50
CYC
CYC
–
–
Address
Address
Page 10 of 34
Fourth
Fourth
A
A
Unit
mA
1
1
ns
ns
ns
ns
11
10
01
00
11
, A
, A
0
0
1
, CE
2
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