CY7C1351G-100AXC Cypress Semiconductor Corp, CY7C1351G-100AXC Datasheet - Page 6

• Manufacturer Part Number: CY7C1351G-100AXC
• Description: IC SRAM 4.5MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1351G-100AXC

• Memory Size: 4.5M (128K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 8 ns
• Maximum Clock Frequency: 100 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 205 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Memory Configuration: 128K X 36
• Clock Frequency: 100MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2117; CY7C1351G-100AXC

reads without reasserting the address inputs. ADV/LD must be
driven LOW in order to load a new address into the SRAM, as
described in the
sequence of the burst counter is determined by the MODE input
signal. A LOW input on MODE selects a linear burst mode, a
HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and will wrap
around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal burst counter regardless of the state
of chip enable inputs or WE. WE is latched at the beginning of a
burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
asserted LOW. The address presented to the address bus is
loaded into the address register. The write signals are latched
into the control logic block. The data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and
DQP
On the next clock rise the data presented to DQs and DQP
(or a subset for byte write operations, see truth table for details)
inputs is latched into the device and the write is complete.
Additional accesses (read/write/deselect) can be initiated on this
cycle.
The data written during the write operation is controlled by
BW
that is described in the truth table. Asserting the write enable
input (WE) with the selected byte write select input will selectively
write to only the desired bytes. Bytes not selected during a byte
write operation will remain unaltered. A synchronous self-timed
write mechanism has been provided to simplify the write
operations. Byte write capability has been included in order to
greatly simplify read/modify/write sequences, which can be
reduced to simple byte write operations.
Because the CY7C1351G is a common I/O device, data should
not be driven into the device while the outputs are active. The
output enable (OE) can be deasserted HIGH before presenting
data to the DQs and DQP
output drivers. As a safety precaution, DQs and DQP
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
ZZ Mode Electrical Characteristics
Document Number: 38-05513 Rev. *H
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
[A:D]
[A:D]
3
signals. The CY7C1351G provides byte write capability
.
are all asserted active, and (3) the write signal WE is
Single Read Accesses
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ inactive to exit sleep current
[A:D]
inputs. Doing so will tri-state the
Description
section above. The
[A:D]
1
, CE
ZZ > V
ZZ > V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
[A:D]
.are
2
,
DD
DD
 0.2 V
Test Conditions
 0.2 V
Burst Write Accesses
The CY7C1351G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
Write operations without reasserting the address inputs. ADV/LD
must be driven LOW in order to load the initial address, as
described in the
ADV/LD is driven HIGH on the subsequent clock rise, the chip
enables (CE
burst counter is incremented. The correct BW
driven in each cycle of the burst write, in order to write the correct
bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
Linear Burst Address Table (MODE = GND)
Interleaved Burst Address Table
(MODE = Floating or V
Address
Address
A1, A0
A1, A0
First
First
00
01
10
00
01
10
11
11
3
, must remain inactive for the duration of t
1
, CE
2
Single Write Accesses
Address
Address
, and CE
Second
Second
A1, A0
A1, A0
01
10
11
00
01
00
11
10
3
) and WE inputs are ignored and the
2t
Min
CYC
DD
–
–
–
0
Address
Address
A1, A0
A1, A0
Third
)
Third
10
00
01
10
00
01
11
11
section above. When
2t
2t
Max
CY7C1351G
40
CYC
CYC
–
–
[A:D]
ZZREC
inputs must be
Address
Address
Fourth
A1, A0
Fourth
A1, A0
Page 6 of 18
11
00
01
10
11
10
01
00
Unit
mA
ns
ns
ns
ns
after the
1
, CE
2
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,