CY7C1351G-100AXC Cypress Semiconductor Corp, CY7C1351G-100AXC Datasheet
CY7C1351G-100AXC
Specifications of CY7C1351G-100AXC
CY7C1351G-100AXC
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CY7C1351G-100AXC Summary of contents
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... The CY7C1351G flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions ...
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... Read/Write Waveforms ............................................. 11 NOP, STALL and DESELECT Cycles ....................... 12 ZZ Mode Timing ........................................................ 12 Ordering Information ...................................................... 13 Ordering Code Definitions ......................................... 13 Package Diagrams .......................................................... 14 Acronyms ........................................................................ 16 Document Conventions ................................................. 16 Units of Measure ....................................................... 16 Document History Page ................................................. 17 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC Solutions ......................................................... 18 CY7C1351G Page [+] Feedback ...
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... Maximum CMOS standby current Pin Configurations DQP DDQ BYTE DDQ DDQ BYTE DDQ DQP 30 D Document Number: 38-05513 Rev. *H 133 MHz 6.5 225 40 100-pin TQFP Pinout CY7C1351G CY7C1351G 100 MHz Unit 8.0 ns 205 DQP DDQ BYTE DDQ DDQ BYTE DDQ DQP A ...
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... Document Number: 38-05513 Rev. *H 119-ball BGA Pinout NC/18M ADV/ DQP NC/ CLK CEN DQP MODE NC/72M Description are fed to the two-bit burst counter. [1:0] to select/deselect the device select/deselect the device select/deselect the device. 2 CY7C1351G DDQ DQP DDQ DDQ DDQ DQP NC/288M NC/36M DDQ Page [+] Feedback ...
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... SRAM is deselected at clock rise by one of the chip enable signals, its output will be tri-stated immediately. Burst Read Accesses , and The CY7C1351G has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four CY7C1351G . During write ...
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... ZZ inactive to exit sleep current RZZI Document Number: 38-05513 Rev. *H Burst Write Accesses The CY7C1351G has an on-chip burst counter that allows the section above. The user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD ...
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... L H None Next Current None [ data when OE is active. [A:D] is valid. Appropriate write will be done based on which byte write is active. X CY7C1351G OE CEN CLK L->H Tri-state L->H Tri-state L->H Tri-state L->H Tri-state L->H Data out ( L->H Data out ( L->H Tri-state L->H Tri-state ...
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... All speeds DD V > < inputs static /2), undershoot: V (AC) > –2 V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1351G + 0 Ambient DDQ Temperature ( °C to +70 °C 3.3 V – 2.5 V – 40 °C to +85 °C Min Max 3.135 3.6 3.135 ...
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... EIA/JESD51 317 3 DDQ GND 351 INCLUDING JIG AND (b) SCOPE R = 1667 2 DDQ GND 1538 INCLUDING JIG AND (b) SCOPE CY7C1351G 100 TQFP 119 BGA Unit Max Max 100 TQFP 119 BGA Unit Package Package 30.32 34.1 °C/W 6.85 14.0 ° ...
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... V. DDQ is the time that the power needs to be supplied above V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1351G –133 –100 Unit Min Max Min Max 1 – 1 – ...
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... D(A2) Q(A3) Q(A4) D(A2+1) t OEHZ t OELZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1351G CHZ Q(A4+1) D(A5) Q(A6) D(A7) t DOH WRITE READ WRITE DESELECT D(A5) Q(A6) D(A7) is LOW HIGH ...
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... A3 A4 Q(A2) Q(A3) STALL READ WRITE STALL Q(A3) D(A4) DON’T CARE UNDEFINED DDZZ High-Z DON’T CARE is LOW. When CE is HIGH HIGH CY7C1351G CHZ D(A4) Q(A5) t DOH NOP READ DESELECT CONTINUE Q(A5) DESELECT t ZZREC t RZZI DESELECT or READ Only is LOW HIGH ...
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... Speed Package (MHz) Ordering Code Diagram 100 CY7C1351G-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free 133 CY7C1351G-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Ordering Code Definitions CY 7C 1351 ...
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... Package Diagrams 100-pin TQFP (14 × 20 × 1.4 mm), 51-85050 Document Number: 38-05513 Rev. *H CY7C1351G 51-85050 *C Page [+] Feedback ...
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... Package Diagrams (continued) Document Number: 38-05513 Rev. *H 119-ball BGA (14 × 22 × 2.4 mm), 51-85115 CY7C1351G 51-85115 *C Page [+] Feedback ...
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... TTL transistor-transistor logic WE write enable Document Number: 38-05513 Rev. *H Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA milli Amperes mm milli meter ms milli seconds MHz Mega Hertz pF pico Farad W Watts °C degree Celcius % percent CY7C1351G Page [+] Feedback ...
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... Document History Page Document Title: CY7C1351G 4-Mbit (128 K × 36) Flow-through SRAM with NoBL™ Architecture Document Number: 38-05513 Orig. of REV. ECN NO. Issue Date Change ** 224360 RKF See ECN *A 276690 See ECN VBL *B 333626 See ECN SYT *C 418633 RXU See ECN *D 480124 ...
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... Document Number: 38-05513 Rev. *H ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised November 29, 2010 CY7C1351G PSoC Solutions psoc.cypress.com/solutions PSoC 1 | ...