CY7C1351G-100AXC Cypress Semiconductor Corp, CY7C1351G-100AXC Datasheet - Page 5

• Manufacturer Part Number: CY7C1351G-100AXC
• Description: IC SRAM 4.5MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1351G-100AXC

• Memory Size: 4.5M (128K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 8 ns
• Maximum Clock Frequency: 100 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 205 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Memory Configuration: 128K X 36
• Clock Frequency: 100MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2117; CY7C1351G-100AXC

Pin Definitions
Functional Overview
The CY7C1351G is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during write-read
transitions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the clock enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. Maximum access delay from the clock rise (t
(133-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
Document Number: 38-05513 Rev. *H
CEN
ZZ
DQ
DQP
MODE
V
V
V
NC
NC/9M,
NC/18M
NC/36M
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
DD
DDQ
SS
Name
s
1
, CE
[A:D]
2
, CE
I/O power supply Power supply for the I/O circuitry.
asynchronous
Power supply
synchronous
synchronous
synchronous
3
) active at the rising edge of the clock. If clock
strap pin
Ground
Input-
Input-
Input
I/O-
I/O-
I/O
–
–
(continued)
[A:D]
can be used to conduct byte write
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin
has an internal pull-down.
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by address during the clock rise of the read cycle. The direction of the pins is controlled
by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs.
When HIGH, DQ
tri-stated during the data portion of a write sequence, during the first clock when emerging from
a deselected state, and when the device is deselected, regardless of the state of OE.
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ
sequences, DQP
Mode input. Selects the burst order of the device. When tied to Gnd selects linear burst
sequence. When tied to V
Power supply inputs to the core of the device.
Ground for the device.
No connects. Not Internally connected to the die.
No connects. Not internally connected to the die. NC/9M,NC/18M,NC/36M,NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the
die.
1
, CE
2
, CE
s
[A:D]
and DQP
CDV
3
is controlled by BW
) and an
) is 6.5 ns
DD
[A:D]
or left floating selects interleaved burst sequence.
are placed in a tri-state condition. The outputs are automatically
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. On the subsequent clock,
another operation (read/write/deselect) can be initiated. When
the SRAM is deselected at clock rise by one of the chip enable
signals, its output will be tri-stated immediately.
Burst Read Accesses
The CY7C1351G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
[A:D]
Description
3
are all asserted active, (3) the write enable input signal
correspondingly.
CY7C1351G
s
. During write
Page 5 of 18
1
, CE
2
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