M24512-RMN6TP STMicroelectronics, M24512-RMN6TP Datasheet - Page 6

IC EEPROM 512KBIT 400KHZ 8SOIC

M24512-RMN6TP

Manufacturer Part Number
M24512-RMN6TP
Description
IC EEPROM 512KBIT 400KHZ 8SOIC
Manufacturer
STMicroelectronics
Datasheets

Specifications of M24512-RMN6TP

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
512K (64K x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Organization
64 K x 8
Interface Type
I2C
Maximum Clock Frequency
0.4 MHz
Access Time
900 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Maximum Operating Current
5 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
2.5 V, 3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-6350-2

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Description
1
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Description
The M24256-Bx devices are I
(EEPROM). They are organized as 32 Kb × 8 bits.
The M24256-Bx and M24256-DR can decode the type identifier code (1010) in accordance
with the I
when accessing the identification page.
The device behaves as a slave in the I
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) (as described in
When writing data to the memory, the device inserts an acknowledge bit during the 9
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Figure 1.
Table 1.
E0, E1, E2
SDA
SCL
WC
V
V
CC
SS
2
Signal name
C bus definition. The M24256-DR also decodes the type identifier code (1011)
Logic diagram
Signal names
Table
2
Doc ID 6757 Rev 21
C-compatible electrically erasable programmable memories
Chip Enable
Serial Data
Serial Clock
Write Control
Supply voltage
Ground
2), terminated by an acknowledge bit.
2
M24256-BF, M24256-BR, M24256-BW, M24256-DR
C protocol, with all memory operations synchronized
Function
Inputs
I/O
Input
Input
Direction
th
bit

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