M24512-RMN6TP STMicroelectronics, M24512-RMN6TP Datasheet - Page 28

• Manufacturer Part Number: M24512-RMN6TP
• Description: IC EEPROM 512KBIT 400KHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M24512-RMN6TP

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 512K (64K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Organization: 64 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-6350-2

DC and AC parameters
28/42
Table 16.
1. All values are referred to V
2. Characterized only, not tested in production.
3. With C
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
5. The new M24xxx-W, M24xxx-R, and M24xxx-BF devices (identified by the process letter K) offer
6. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
7. t
8. The current M24xxx devices (identified by the Process letter A) offer t
t
t
CLQV
QL1QL2
Symbol
t
t
XH1XH2
XL1XL2
t
t
t
t
t
t
t
t
t
DXCX
CHDH
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
t
t
specification which recommends t
rising edge of SDA.
0.7V
BR and M24256-DR device (identified by the process letter K) offer t
safe margin compared to the 50 ns minimum value recommended by the I
CHCL
CLCH
CLDX
CLQX
CHDL
DHDL
DLCL
C
CLQX
CLQX
CLQV
t
t
f
NS
W
C
< 400 kHz.
(6)(7)
CC
(2)
= 200 ns (min) and t
= 100 ns (min) and t
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3V
L
, assuming that R
= 10 pF.
t
t
t
t
t
SU:STO
SU:DAT
HD:DAT
SU:STA
HD:STA
400 kHz AC characteristics
t
t
f
t
Test conditions specified in
HIGH
Alt.
t
LOW
t
t
BUF
SCL
WR
t
DH
t
t
AA
R
F
F
Clock frequency
Clock pulse width high
Clock pulse width low
SDA (out) fall time
Input signal rise time
Input signal fall time
Data in set up time
Data in hold time
Data out hold time
Clock low to next data valid (access time)
Start condition setup time
Start condition hold time
Stop condition set up time
Time between Stop condition and next Start
condition
Write time
Pulse width ignored (input filter on SCL and
SDA) - single glitch
bus
CLQV
CLQV
IL
(max) and V
× C
= 200 ns (min). Both series offer a safe margin compared to the I
= 100 ns (min), while the current devices (process letter A) offer
bus
CLQV
Doc ID 6757 Rev 21
time constant is within the values specified in
= 0 ns (min).
IH
Parameter
(min).
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table
8,
Table
9,
Table 10
NS
NS
=80 ns (min). Both products offer a
=100 ns (min), the new M24256-
2
C specification.
and
Min.
100
100
1300
1300
20
600
100
600
600
600
(4)
(4)
0
Figure
(3)
(5)
(5)
Table 11
(1)
6.
Max.
80
400
120
900
(4)
(4)
5
(8)
(1)
2
CC
C
or
Unit
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns