M24512-WMN6TP STMicroelectronics, M24512-WMN6TP Datasheet - Page 27

• Manufacturer Part Number: M24512-WMN6TP
• Description: IC EEPROM 512KBIT 400KHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M24512-WMN6TP

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 512K (64K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Density: 512Kb
• Interface Type: Serial (I2C)
• Organization: 64Kx8
• Access Time (max): 900ns
• Frequency (max): 400KHz
• Write Protection: Yes
• Data Retention: 40Year
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: -40C to 85C
• Supply Current: 5mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8626-2; M24512-WMN6TP

M24512-R, M24512-W, M24512-DR
Table 14.
1. All values are referred to V
2. Characterized only, not tested in production.
3. With C
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
5. The I²C-bus specification does not define a min value for the data hold time (tHD;DAT). The min value for
6. t
t
QL1QL2
Symbol
t
t
t
t
XH1XH2
CLQX
CLQV
XL1XL2
t
t
t
t
t
t
t
t
t
DXCX
CHDH
I²C specification that the input signal rise and fall times be less than 120 ns when f
t
falling edge SCL.
0.7 V
CHCL
CLCH
CLDX
CHDL
DHDL
DLCL
NS
CLQX
CLQV
t
f
W
C
(2)
(5)
(6)
CC
(2)
(Data out hold time) of the M24xxx devices offers a safe timing to bridge the undefined region of the
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 V
L
, assuming that R
= 10 pF.
t
t
t
t
t
SU:STO
SU:DAT
HD:DAT
SU:STA
HD:STA
400 kHz AC characteristics
t
t
f
t
HIGH
Alt.
t
LOW
t
t
BUF
SCL
WR
t
DH
t
t
AA
R
F
F
Test conditions specified in
Clock frequency
Clock pulse width high
Clock pulse width low
SDA (out) fall time
Input signal rise time
Input signal fall time
Data in set up time
Data in hold time
Data out hold time
Clock low to next data valid (access time)
Start condition setup time
Start condition hold time
Stop condition set up time
Time between Stop condition and next Start
condition
Write time
Pulse width ignored (input filter on SCL and
SDA) - single glitch
bus
IL
(max) and V
× C
bus
Doc ID 16459 Rev 22
time constant is within the values specified in
IH
Parameter
(min).
Table
8,
Table 9
and
Table 10
Min.
1300
1300
20
600
100
100
600
600
600
DC and AC parameters
(4)
(4)
0
(3)
Figure
C
(1)
< 1 MHz..
6.
Max.
400
120
900
80
(4)
(4)
5
(1)
CC
or
Unit
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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