M24512-WMN6TP STMicroelectronics, M24512-WMN6TP Datasheet - Page 21

• Manufacturer Part Number: M24512-WMN6TP
• Description: IC EEPROM 512KBIT 400KHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M24512-WMN6TP

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 512K (64K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Density: 512Kb
• Interface Type: Serial (I2C)
• Organization: 64Kx8
• Access Time (max): 900ns
• Frequency (max): 400KHz
• Write Protection: Yes
• Data Retention: 40Year
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: -40C to 85C
• Supply Current: 5mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8626-2; M24512-WMN6TP

M24512-R, M24512-W, M24512-DR
3.16
3.17
3.18
Current Address Read (in memory array)
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
Read Identification Page
The Identification Page can be read by issuing an ID Read instruction. This instruction uses
the same protocol and format as the Random Address Read (from memory array) with the
device type identifier defined as 1011b. The MSB address bits A17 to A7 are “don’t care”.
The LSB address bits A6 to A0 define the byte address inside the Identification Page. The
number of bytes to read in the ID page must not exceed the page boundary (e.g. when
reading the Identification Page from location 100d, the number of bytes should be less than
or equal to 28, as the ID page boundary in 128 bytes). If the Identification Page is locked,
the data bytes are read as FFh.
10, without acknowledging the byte.
Figure
Doc ID 16459 Rev 19
10.
Device operation
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