M24C02-WBN6P STMicroelectronics, M24C02-WBN6P Datasheet - Page 8

• Manufacturer Part Number: M24C02-WBN6P
• Description: IC EEPROM 2KBIT 400KHZ 8DIP
• Manufacturer: STMicroelectronics

Specifications of M24C02-WBN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 6.5 V
• Capacitance, Input: 8 pF (SDA), 6 pF (Other Pins)
• Current, Input, Leakage: ±2 μA
• Current, Operating: 2 mA
• Current, Output, Leakage: ±2
• Data Retention: >40 yrs.
• Density: 2K
• Package Type: PDIP8
• Temperature, Operating: -40 to +85 °C
• Time, Access: 900 ns
• Time, Fall: 50 ns
• Time, Rise: 50 ns
• Voltage, Esd: 4000 V
• Voltage, Input, High: 3.5 to 6.5 V
• Voltage, Input, Low: 0.75 to 1.65 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 2.5 to 5.5 V
• Memory Configuration: 256 X 8
• Clock Frequency: 400kHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: DIP
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8584-5; M24C02-WBN6P

M24C16, M24C08, M24C04, M24C02, M24C01
DEVICE OPERATION
The device supports the I²C protocol. This is sum-
marized in
on to the bus is defined to be a transmitter, and
any device that reads the data to be a receiver.
The device that controls the data transfer is known
as the bus master, and the other as the slave de-
vice. A data transfer can only be initiated by the
bus master, which will also provide the serial clock
for synchronization. The M24Cxx device is always
a slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal Write
cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During the
9
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
8/28
th
clock pulse period, the receiver pulls Serial
Figure
6.. Any device that sends data
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is driv-
en Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1010b.
Each device is given a unique 3-bit code on the
Chip Enable (E0, E1, E2) inputs. When the Device
Select Code is received, the device only responds
if the Chip Enable Address is the same as the val-
ue on the Chip Enable (E0, E1, E2) inputs. How-
ever, those devices with larger memory capacities
(the M24C16, M24C08 and M24C04) need more
address bits. E0 is not available for use on devices
that need to use address line A8; E1 is not avail-
able for devices that need to use address line A9,
and E2 is not available for devices that need to use
address line A10 (see
details). Using the E0, E1 and E2 inputs, up to
eight M24C02 (or M24C01), four M24C04, two
M24C08 or one M24C16 devices can be connect-
ed to one I²C bus. In each case, and in the hybrid
cases, this gives a total memory capacity of
16 Kbits, 2 KBytes (except where M24C01 devic-
es are used).
The 8
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
th
bit is the Read/Write bit (RW). This bit is
Figure 3.
and
th
bit time. If the
Table 3.
Table 3.
for