M95010-WMN6TP STMicroelectronics, M95010-WMN6TP Datasheet - Page 22
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M95010-WMN6TP
Manufacturer Part Number
M95010-WMN6TP
Description
IC EEPROM 1KBIT 10MHZ 8SOIC
Manufacturer
STMicroelectronics
Datasheet
1.M95010-WMN6TP.pdf
(43 pages)
Specifications of M95010-WMN6TP
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
1K (128 x 8)
Speed
10MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Density
1Kb
Interface Type
Serial (SPI)
Organization
128x8
Access Time (max)
35ns
Frequency (max)
10MHz
Write Protection
Yes
Data Retention
40Year
Operating Supply Voltage (typ)
3.3/5V
Package Type
SOIC
Operating Temp Range
-40C to 85C
Supply Current
2mA
Operating Supply Voltage (min)
2.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Maximum Clock Frequency
5 MHz
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
2 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8672-2
M95010-WMN6TP
M95010-WMN6TP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M95010-WMN6TP
Manufacturer:
TI
Quantity:
21 000
Part Number:
M95010-WMN6TP
Manufacturer:
ST
Quantity:
20 000
Instructions
6.6
Note:
22/43
Write to Memory Array (WRITE)
As shown in
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data input (D). The instruction is terminated by driving Chip Select (S) high at a
byte boundary of the input data. The self-timed Write cycle, triggered by the rising edge of
Chip Select (S), continues for a period t
time, the Write in Progress (WIP) bit is reset to 0.
In the case of
has been latched in, indicating that the instruction is being used to write a single byte. If,
though, Chip Select (S) continues to be driven low, as shown in
input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle. If Chip
Select (S) still continues to be driven low, the next byte of input data is shifted in, and used to
overwrite the byte at the start of the current page.
The instruction is not accepted, and is not executed, under the following conditions:
●
●
●
●
The self-timed write cycle t
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 12. Byte Write (WRITE) sequence
1. Depending on the memory size, as shown in
S
C
D
Q
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
if a Write cycle is already in progress
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the rising edge of Serial Clock (C) that latches the last data bit, and
before the next rising edge of Serial Clock (C) occurs anywhere on the bus)
if Write Protect (W) is low or if the addressed page is in the area protected by the Block
Protect (BP1 and BP0) bits
Figure
0
Figure
1
High Impedance
2
12, to send this instruction to the device, Chip Select (S) is first driven
Instruction
12, Chip Select (S) is driven high after the eighth bit of the data byte
3
A8
4
W
5
is internally executed as a sequence of two consecutive
6
Doc ID 6512 Rev 8
7
A7
8
A6 A5 A4 A3 A2 A1 A0
9 10 11 12 13 14 15 16 17 18 19
Table
W
Byte Address
(as specified in
6, the most significant address bits are Don’t Care.
Table 13
7
6
Figure
M95040, M95020, M95010
5
Data Byte
to
4
Table
3
20 21 22 23
13, the next byte of
2
20). After this
1
0
AI01442D