M95010-WMN6TP STMicroelectronics, M95010-WMN6TP Datasheet - Page 21
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M95010-WMN6TP
Manufacturer Part Number
M95010-WMN6TP
Description
IC EEPROM 1KBIT 10MHZ 8SOIC
Manufacturer
STMicroelectronics
Datasheet
1.M95010-WMN6TP.pdf
(43 pages)
Specifications of M95010-WMN6TP
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
1K (128 x 8)
Speed
10MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Density
1Kb
Interface Type
Serial (SPI)
Organization
128x8
Access Time (max)
35ns
Frequency (max)
10MHz
Write Protection
Yes
Data Retention
40Year
Operating Supply Voltage (typ)
3.3/5V
Package Type
SOIC
Operating Temp Range
-40C to 85C
Supply Current
2mA
Operating Supply Voltage (min)
2.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Maximum Clock Frequency
5 MHz
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
2 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8672-2
M95010-WMN6TP
M95010-WMN6TP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M95010-WMN6TP
Manufacturer:
TI
Quantity:
21 000
Part Number:
M95010-WMN6TP
Manufacturer:
ST
Quantity:
20 000
M95040, M95020, M95010
6.5
Read from Memory Array (READ)
As shown in
low. The bits of the instruction byte and address byte are then shifted in, on Serial Data Input
(D). For the M95040, the most significant address bit, A8, is incorporated as bit b3 of the
instruction byte, as shown in
register, and the byte of data at that address is shifted out, on Serial Data Output (Q).
If Chip Select (S) continues to be driven low, an internal bit-pointer is automatically
incremented at each clock cycle, and the corresponding data bit is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Table 6.
Figure 11. Read from Memory Array (READ) sequence
1. Depending on the memory size, as shown in
Address Bits
S
C
D
Q
Device
Figure
Address range bits
0
1
11, to send this instruction to the device, Chip Select (S) is first driven
High Impedance
2
Instruction
3
A8
4
Table
5
Doc ID 6512 Rev 8
M95040
6
A8-A0
4. The address is loaded into an internal address
7
A7
Table
8
A6 A5 A4 A3 A2 A1 A0
9 10 11 12 13 14 15 16 17 18 19
6, the most significant address bits are Don’t Care.
Byte Address
M95020
A7-A0
7
6
5
Data Out
4
3
20 21 22
2
M95010
A6-A0
Instructions
1
0
AI01440E
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