C8051T323-GMR Silicon Labs, C8051T323-GMR Datasheet - Page 186
C8051T323-GMR
Manufacturer Part Number
C8051T323-GMR
Description
8-bit Microcontrollers - MCU USB-OTP-16K-QFN28
Manufacturer
Silicon Labs
Datasheet
1.C8051T322-GQR.pdf
(292 pages)
Specifications of C8051T323-GMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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C8051T620/621/320/321/322/323
USB Register Definition 23.23. EOUTCSRH: USB0 OUT Endpoint Control High
Byte
USB Register Address = 0x15
USB Register Definition 23.24. EOUTCNTL: USB0 OUT Endpoint Count Low
USB Register Address = 0x16
186
Name
Reset
Name
Reset
Bit
5:0
Bit
7:0 EOCL[7:0] OUT Endpoint Count Low Byte.
Type
Type
7
6
Bit
Bit
DBOEN
Unused
Name
Name
ISO
DBOEN
R/W
7
0
7
0
Double-buffer Enable.
0: Double-buffering disabled for the selected OUT endpoint.
1: Double-buffering enabled for the selected OUT endpoint.
Isochronous Transfer Enable.
This bit enables/disables isochronous transfers on the current endpoint.
0: Endpoint configured for bulk/interrupt transfers.
1: Endpoint configured for isochronous transfers.
Unused. Read = 000000b. Write = don’t care.
EOCL holds the lower 8-bits of the 10-bit number of data bytes in the last received
packet in the current OUT endpoint FIFO. This number is only valid while OPRDY = 1.
R/W
ISO
6
0
6
0
R
5
0
5
0
Rev. 1.1
R
4
0
4
0
EOCL[7:0]
R
Function
Function
R
3
0
3
0
R
2
0
2
0
R
1
0
1
0
R
0
0
0
0
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