S9S08DZ60F2MLF Freescale Semiconductor, S9S08DZ60F2MLF Datasheet - Page 383

• Manufacturer Part Number: S9S08DZ60F2MLF
• Description: 8-bit Microcontrollers - MCU M74K MASK ONLY-AUTO
• Manufacturer: Freescale Semiconductor

Specifications of S9S08DZ60F2MLF

• Rohs: yes
• Core: HCS08
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 60 KB
• Data Ram Size: 4 K
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• Processor Series: MC9S08DZ60

1
2
3
4
A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1
Freescale Semiconductor
Typical data was characterized at 5.0 V, 25°C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
When any reset is initiated, internal circuitry drives the RESET pin low for about 34 cycles of t
clock frequency changes to the untrimmed DCO frequency (freset = (f
reset to 0; and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets, trim stays at the pre-reset value.
Timing is shown with respect to 20% V
Nu
m
1
2
3
4
5
6
7
8
D/
D
D
D
D
D
P
T
T
C
Control Timing
Bus frequency (t
Internal low-power oscillator period
External reset pulse width
Reset low drive
Active background debug mode latch setup time
Active background debug mode latch hold time
IRQ/PIAx/ PIBx/PIDx pulse width
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Asynchronous path
Synchronous path
RESET PIN
Slew rate control disabled (PTxSE = 0)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
Slew rate control enabled (PTxSE = 1)
3
cyc
= 1/f
3
2
Rating
Bus
2
DD
)
MC9S08DZ60 Series Data Sheet, Rev. 4
and 80% V
Table A-13. Control Timing
Figure A-2. Reset Timing
DD
levels. Temperature range –40°C to 125°C.
4
4
t
extrst
t
t
t
dco_ut
Rise
Rise
Symbol
ILIH,
t
t
t
MSSU
t
t
rstdrv
f
extrst
MSH
LPO
Bus
, t
, t
t
IHIL
)/4) because TRIM is reset to 0x80 and FTRIM is
Fall
Fall
1.5 x t
34 x t
1.5 t
100
Min
dc
—
25
25
—
—
—
—
cyc
cyc
cyc
Appendix A Electrical Characteristics
cyc
Typical
. After POR reset, the bus
1500
40
75
11
35
—
—
1
Max
20
—
—
—
—
—
—
MHz
Unit
μs
ns
ns
ns
ns
ns
ns
ns
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