MT48LC32M16A2P-75:C TR Micron Technology Inc, MT48LC32M16A2P-75:C TR Datasheet - Page 65

• Manufacturer Part Number: MT48LC32M16A2P-75:C TR
• Description: IC SDRAM 512MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC32M16A2P-75:C TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 115mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1078-2

Figure 49:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
DQML, DQMU
COMMAND
A11, A12
BA0, BA1
A0–A9,
DQM/
A10
CLK
CKE
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
BANK 0
Alternating Bank WRITE Accesses
T0
ROW
ROW
t CKH
t CMH
t AH
t AH
t AH
Notes:
t RCD - BANK 0
t RAS - BANK 0
t
t
RC - BANK 0
RRD
t CK
T1
NOP
1. For this example, BL = 4.
2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns
3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
ENABLE AUTO PRECHARGE
with PRECHARGE.
t CMS
t CL
t DS
COLUMN m 3
BANK 0
WRITE
T2
D
IN
t CMH
t CH
t DH
m
t DS
D
IN
T3
NOP
m + 1
t DH
t DS
D
BANK 1
ACTIVE
IN
T4
ROW
ROW
m + 2
65
t DH
t RCD - BANK 1
t DS
D
IN
T5
NOP
m + 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DH
t WR - BANK 0
ENABLE AUTO PRECHARGE
t DS
COLUMN b 3
BANK 1
WRITE
T6
D
IN
t DH
b
512Mb: x4, x8, x16 SDRAM
t DS
D
NOP
IN
T7
b + 1
t DH
©2000 Micron Technology, Inc. All rights reserved.
t DS
t RP - BANK 0
Timing Diagrams
D
IN
NOP
T8
b + 2
t DH
t DS
D
BANK 0
ACTIVE
T9
ROW
IN
ROW
b + 3
t
t
RCD - BANK 0
WR - BANK 1
t DH
Don’t Care