IS61NLF102418-7.5TQLI-TR ISSI, IS61NLF102418-7.5TQLI-TR Datasheet - Page 22

• Manufacturer Part Number: IS61NLF102418-7.5TQLI-TR
• Description: SRAM 18Mb, 3.3v, 7.5ns 1Mb x 18 Sync SRAM
• Manufacturer: ISSI
• Type: Synchronous Flow-Through SRAMr

Specifications of IS61NLF102418-7.5TQLI-TR

• Memory Size: 18 MB
• Organization: 1 M x 18
• Access Time: 7.5 ns
• Supply Voltage - Max: 3.3 V
• Supply Voltage - Min: 2.5 V
• Maximum Operating Current: 425 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Maximum Clock Frequency: 117 MHz
• Memory Type: Synchronous

IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
The IS61NLFX and IS61NVFX have a serial boundary
scan Test Access Port (TAP) in the PBGA package only.
(Not available in TQFP package.) This port operates in
accordance with IEEE Standard 1149.1-1900, but does not
include all functions required for full 1149.1 compliance.
These functions from the IEEE specification are excluded
because they place added delay in the critical speed path
of the SRAM. The TAP controller operates in a manner that
does not conflict with the performance of other devices us-
ing 1149.1 fully compliant TAPs. The TAP operates using
JEDEC standard 2.5V I/O logic levels.
DISABLING THE JTAG FEATURE
The SRAM can operate without using the JTAG feature.
To disable the TAP controller, TCK must be tied LOW
(V
internally pulled up and may be disconnected. They may
alternately be connected to V
TDO should be left disconnected. On power-up, the device
will start in a reset state which will not interfere with the
device operation.
TAP CONTROLLER BLOCK DIAGRAM
22
SS
) to prevent clocking of the device. TDI and TMS are
TMS
TCK
TDI
Selection Circuitry
TAP CONTROLLER
dd
through a pull-up resistor.
31 30 29
0
2
x
Bypass Register
Instruction Register
Identification Register
Boundary Scan Register*
. . . . .
1
Integrated Silicon Solution, Inc. — www.issi.com —
0
. . .
TEST ACCESS PORT (TAP) - TEST CLOCK
The test clock is only used with the T AP controller. All inputs
are captured on the rising edge of TCK and outputs are
driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The
pin is internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information to the
registers and can be connected to the input of any regis-
ter. The register between TDI and TDO is chosen by the
instruction loaded into the TAP instruction register. For
information on instruction register loading, see the TAP
Controller State Diagram. TDI is internally pulled up and
can be disconnected if the TAP is unused in an applica-
tion. TDI is connected to the Most Significant Bit (MSB)
on any register.
2
2
1
1
0
0
Selection Circuitry
1-800-379-4774
TDO
04/11/12
Rev. D