IS61WV12816EDBLL-10TLI ISSI, IS61WV12816EDBLL-10TLI Datasheet - Page 8

• Manufacturer Part Number: IS61WV12816EDBLL-10TLI
• Description: SRAM 2Mb (128K x 16) 10ns 2.4V-3.6V
• Manufacturer: ISSI

Specifications of IS61WV12816EDBLL-10TLI

• Rohs: yes
• Memory Size: 2 Mbit
• Organization: 128 Kbit x 16
• Access Time: 10 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.4 V
• Maximum Operating Current: 35 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TSOP-44
• Memory Type: Asynchronous CMOS
• Factory Pack Quantity: 135

IS61/64WV12816EDBLL
WRITE CYCLE SWITCHING CHARACTERISTICS
8
Symbol
Notes:
1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
t
t
t
t
t
t
t
t
t
t
t
t
wc
sce
aw
Ha
sa
Pwb
Pwe
Pwe
sd
Hd
Hzwe
Lzwe
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the write. Shaded area product in development
1
2
(2)
(2)
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
6.5 —
6.5 —
6.5 —
6.5 —
Min. Max.
— 3.5
8 —
0 —
0 —
8 —
5 —
0 —
2 —
-8
(1,3)
10 —
8 —
8 —
0 —
0 —
8 —
8 —
10 —
6 —
0 —
— 5
2 —
Min. Max.
(Over Operating Range)
Integrated Silicon Solution, Inc. — www.issi.com
-10
Min.
20 —
12 —
12 —
12 —
12 —
17 —
—
0 —
0 —
9 —
0 —
3 —
-20
Max.
9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
n s
ns
ns
09/29/2011
Rev. A