IS61WV5128BLL-10TLI ISSI, Integrated Silicon Solution Inc, IS61WV5128BLL-10TLI Datasheet - Page 15
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IS61WV5128BLL-10TLI
Manufacturer Part Number
IS61WV5128BLL-10TLI
Description
IC SRAM 4MBIT 10NS 44TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
Asynchronousr
Datasheet
1.IS61WV5128BLL-10TLI.pdf
(25 pages)
Specifications of IS61WV5128BLL-10TLI
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Memory Size
4M (512K x 8)
Speed
10ns
Interface
Parallel
Voltage - Supply
1.65 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TSOP II
Access Time
10 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.4 V
Maximum Operating Current
40 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
2.5 V, 3.3 V
Density
4Mb
Access Time (max)
10ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
2.5/3.3V
Address Bus
19b
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Supply Current
40mA
Operating Supply Voltage (min)
2.4V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Word Size
8b
Number Of Words
512K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
706-1108
IS61WV5128BLL-10TLI
Q4714568
IS61WV5128BLL-10TLI
Q4714568
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS61WV5128BLL-10TLI
Manufacturer:
ISSI
Quantity:
675
Company:
Part Number:
IS61WV5128BLL-10TLI
Manufacturer:
PANASONIC
Quantity:
2 606
Part Number:
IS61WV5128BLL-10TLI
Manufacturer:
ISSI
Quantity:
20 000
WRITE CYCLE NO. 3
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
WRITE CYCLE NO. 2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
2. I/O will assume the High-Z state if OE > V
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
ADDRESS
ADDRESS
D
D
OUT
OUT
WE
WE
D
D
OE
OE
CE
CE
IN
IN
LOW
LOW
LOW
t
SA
(1,2)
(WE Controlled: OE is LOW During Write Cycle)
t
DATA UNDEFINED
DATA UNDEFINED
SA
(WE Controlled: OE is HIGH During Write Cycle)
Ih
.
VALID ADDRESS
t
t
t
t
AW
AW
HZWE
HZWE
VALID ADDRESS
t
t
PWE1
WC
t
t
PWE2
WC
HIGH-Z
HIGH-Z
t
t
SD
SD
DATA
DATA
IN
IN
VALID
VALID
t
t
HD
HD
t
t
LZWE
LZWE
t
t
HA
HA
CE_WR2.eps
CE_WR3.eps
15