IS42S16400D-7TL ISSI, Integrated Silicon Solution Inc, IS42S16400D-7TL Datasheet - Page 4

• Manufacturer Part Number: IS42S16400D-7TL
• Description: IC SDRAM 64MBIT 143MHZ 54TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S16400D-7TL

• Package / Case: 54-TSOP II
• Memory Size: 64M (4M x 16)
• Format - Memory: RAM
• Memory Type: SDRAM
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Data Bus Width: 16 bit
• Organization: 1 Mbit x 16
• Maximum Clock Frequency: 143 MHz
• Access Time: 7 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 100 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 706-1019

IS42S16400D
PIN FUNCTIONS
4
BA0, BA1
Symbol
A0-A11
DQ0 to
LDQM,
UDQM
GND
DQ15
CAS
CKE
V
GND
CLK
RAS
V
WE
CS
DDQ
DD
Q
11,13, 42, 44, 45,
47, 48, 50, 51, 53
2, 4, 5, 7, 8, 10,
TSOP Pin No.
6, 12, 46, 52
3, 9, 43, 49
28, 41, 54
1, 14, 27
23 to 26
29 to 34
22, 35
15, 39
20, 21
17
37
38
19
18
16
Power Supply Pin V
Power Supply Pin V
Power Supply Pin GND
Power Supply Pin GND is the device internal ground.
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
DQ Pin
Type
Function (In Detail)
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (A0-A7
with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When
CKE is LOW, the device will be in either power-down mode, clock suspend mode,
or self refresh mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
DQ0 to DQ15 are I/O pins. I/O through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the
HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE
in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer.
When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can
be written to the device. When LDQM or UDQM is HIGH, input data is masked and
cannot be written to the device.
RAS, in conjunction with CAS and WE, forms the device command. See the "Command
Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Command
Truth Table" item for details on device commands.
DDQ
DD
is the device internal power supply.
Q
is the output buffer power supply.
is the output buffer ground.
Integrated Silicon Solution, Inc. — www.issi.com
11/21/07
Rev. E