IS61LV6416-10TL ISSI, Integrated Silicon Solution Inc, IS61LV6416-10TL Datasheet - Page 7

IC SRAM 1MBIT 10NS 44TSOP

IS61LV6416-10TL

Manufacturer Part Number
IS61LV6416-10TL
Description
IC SRAM 1MBIT 10NS 44TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
Asynchronousr
Datasheet

Specifications of IS61LV6416-10TL

Memory Size
1M (64K x 16)
Package / Case
44-TSOP II
Interface
Parallel
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Speed
10ns
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Access Time
10 ns
Supply Voltage (max)
3.63 V
Supply Voltage (min)
3.135 V
Maximum Operating Current
120 mA
Organization
64 K x 16
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1039

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS61LV6416-10TL
Manufacturer:
ISSI
Quantity:
121
Part Number:
IS61LV6416-10TL
Manufacturer:
ISSI
Quantity:
20 000
Part Number:
IS61LV6416-10TL1
Manufacturer:
ISSI
Quantity:
20 000
Part Number:
IS61LV6416-10TLI
Manufacturer:
ISSI
Quantity:
1 000
Part Number:
IS61LV6416-10TLI
Manufacturer:
HAR
Quantity:
100
Part Number:
IS61LV6416-10TLI
Manufacturer:
ISSI
Quantity:
1 000
Part Number:
IS61LV6416-10TLI
Manufacturer:
ISSI
Quantity:
20 000
Part Number:
IS61LV6416-10TLI
0
IS61LV6416
IS61LV6416L
Integrated Silicon Solution, Inc.
Rev. I
11/22/05
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
Symbol
t
t
t
t
t
t
t
t
t
t
t
output loading specified in Figure 1a.
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
WC
SCE
HA
SD
HD
HZWE
LZWE
AW
SA
PBW
PWE
1
(2)
(2)
/
t
PWE
2
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width (OE = HIGH/LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
Min. Max.
8
6
8
0
0
7
6
6
0
3
-8 ns
4
(1,3)
(Over Operating Range)
Min. Max.
10
8
8
0
0
8
8
6
0
3
-10 ns
5
Min. Max.
12
9
9
0
0
9
9
6
0
3
-12 ns
6
ISSI
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
®
1
2
3
4
5
6
7
8
9
10
11
12

Related parts for IS61LV6416-10TL