BR24L64F-WE2 Rohm Semiconductor, BR24L64F-WE2 Datasheet - Page 27
![IC EEPROM 64KBIT 400KHZ 8SOP](/photos/7/22/72233/br24l64f-we2_sml.jpg)
BR24L64F-WE2
Manufacturer Part Number
BR24L64F-WE2
Description
IC EEPROM 64KBIT 400KHZ 8SOP
Manufacturer
Rohm Semiconductor
Specifications of BR24L64F-WE2
Memory Size
64K (8K x 8)
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOP
Clock Frequency
400kHz
Supply Voltage Range
1.8V To 5.5V
Memory Case Style
SOP
No. Of Pins
8
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (18-Jun-2010)
Package /
RoHS Compliant
Organization
8 Kbit x 8
Interface Type
I2C
Maximum Clock Frequency
0.1 MHz
Access Time
3500 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Maximum Operating Current
3 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V, 5.5 V
Memory Configuration
8K X 8
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
BR24L64F-WE2
BR24L64F-WE2TR
BR24L64F-WE2TR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
BR24L64F-WE2
Manufacturer:
ROMH
Quantity:
2 296
Part Number:
BR24L64F-WE2
Manufacturer:
ROHM/罗姆
Quantity:
20 000
●WP valid timing (write cancel)
●Command cancel by start condition and stop condition
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid
timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write
cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data(in page
write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken 100ns or more. The area from the rise of SCL
to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR, write is
ended forcibly, data of address under access is not guaranteed, therefore, write it once again.(Refer to Fig.47.) After
execution of forced end by WP standby status gets in, so there is no need to wait for tWR (5ms at maximum).
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to Fig.
48.)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
SDA
SCL
Fig.48 Case of cancel by start, stop condition during slave address input
SDA
WP
S
T
A
R
T
SDA
SCL
address
・Rise of D0 taken clock
Sl a ve
1
C
A
K
L
Enlarged view
WP cancel invalid area
address
Word
D1
0
A
C
K
L
D0
D7 D6 D5 D4 D3 D2 D1 D0
ACK
1
Fig.47 WP valid timing
27/32
0
Start condition
Data is not written.
WP cancel valid area
A
C
K
L
SDA
SCL
Data
Stop condition
D0
・Rise of SDA
C
A
K
L
Enlarged view
ACK
O
S
T
P
Data not guaranteed
Write forced end
tWR