BR24S64FVT-WE2 Rohm Semiconductor, BR24S64FVT-WE2 Datasheet - Page 27
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BR24S64FVT-WE2
Manufacturer Part Number
BR24S64FVT-WE2
Description
IC EEPROM 64KBIT 400KHZ 8TSSOP
Manufacturer
Rohm Semiconductor
Datasheet
1.BR24L01AFV-WE2.pdf
(41 pages)
Specifications of BR24S64FVT-WE2
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
64K (8K x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-TSSOP-B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
BR24S64FVT-WE2TR
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© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
www.rohm.com
2
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is 'HIGH'
○I
○Start condition (start bit recognition)
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is
○Stop condition (stop bit recognition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master
・The device (this IC at slave address input of write command, read command, and μ-COM at data output of read
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this IC
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'.
・Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same bus
・The most insignificant bit (R/W --- READ/WRITE) of slave address is used for designating write or read action, and is as
C BUS communication
and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data output of read
command) at the transmitter (sending) side releases the bus after output of 8bit data.
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes
stop condition (stop bit), and ends read action. And this IC gets in standby status.
according to the number of device addresses.
shown below.
is necessary.
satisfied, any command is executed.
P0~P2 are page select bits.
Note) Up to 2 units of BR24S08-W, up to 1 units of BR24S16-W, and up to 8 units of BR24S32/64/128/256-W can be connected.
BR24S08-W
BR24S16-W
BR24S32-W, BR24S64-W
BR24S128-W, BR24S256-W
2
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and acknowledge is always required after each byte.
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serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by addresses peculiar to devices.
EEPROM becomes “slave”. And the device that outputs data to bus during data communication is called “transmitter”,
and the device that receives data is called “receiver”.
Setting R/W to 0 --- write (setting 0 to word address setting of random read)
Setting R/W to 1 --- read
C BUS data communication
2
2
C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and
Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.
Type
SDA
SCL
START
condition
S
ADDRESS
1-7
1 0 1 0 A2 P1 P0 R/W
1 0 1 0 P2 P1 P0 R/W
1 0 1 0 A2 A1 A0 R/W
R/W
8
Fig.32 Data transfer timing
Slave address
ACK
9
1-7
DATA
27/40
8
ACK
9
―
―
―
1-7
DATA
Maximum number of
connected buses
8
2
1
8
ACK
9
condition
STOP
P
A0
A1
A2
GND
1
2
3
4
BR24S08-W
BR24S16-W
BR24S32-W
BR24S64-W
BR24S128-W
BR24S256-W
Technical Note
2009.09 - Rev.D
8
7
6
5
Vcc
WP
SCL
SDA