BR24S64FVT-WE2 Rohm Semiconductor, BR24S64FVT-WE2 Datasheet - Page 16
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BR24S64FVT-WE2
Manufacturer Part Number
BR24S64FVT-WE2
Description
IC EEPROM 64KBIT 400KHZ 8TSSOP
Manufacturer
Rohm Semiconductor
Datasheet
1.BR24L01AFV-WE2.pdf
(41 pages)
Specifications of BR24S64FVT-WE2
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
64K (8K x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-TSSOP-B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
BR24S64FVT-WE2TR
●I/O peripheral circuit
●A0, A1, A2, WP process
© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
www.rohm.com
○Pull up resistance of SDA terminal
○Maximum value of R
○Minimum value of R
○Pull up resistance of SCL terminal
○Process of device address terminals (A0,A1,A2)
○Process of WP terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (R
this resistance value from microcontroller V
limited. The smaller the R
The maximum value of R
(1)SDA rise time to be determined by the capacitance (CBUS) of bus line of R
(2)The bus electric potential
Ex. ) When V
from (2)
The minimum value of R
(1)When IC outputs LOW, it should be satisfied that V
(2)V
Therefore, the condition (2) is satisfied.
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ ~ several ten kΩ is recommended in
consideration of drive performance of output port of microcontroller.
Check whether the set device address coincides with device address input sent from the master side or not, and select
one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or Vcc or GND. And,
pins (N, C, PIN) not used as device address may be set to any of 'H' , 'L', and 'Hi-Z'.
WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and
WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is
recommended to connect it to pull up or Vcc. In the case to use both READ and WRITE, control WP terminal or connect
it to pull down or GND.
And AC timing should be satisfied even when SDA rise time is late.
SDA bus and R
recommended noise margin 0.2Vcc.
∴ R
V
Ex. ) When V
R
OLMAX
OLMAX
V
from (1)
Types with N.C.PIN
PU
CC
PU
=0.4V should secure the input 'L' level (V
≦
- I
L
≦ V
R
CC
0.8×3-0.7×3
=
And
PU
V
10×10
=3V, I
CC
CC
PU
IL
- 0.2Vcc ≧ V
R
0.8Vcc-V
PU
-0.1 V
PU
-V
PU
should sufficiently secure the input 'H' level (V
=3V, V
R
≦ 300 [kΩ]
OL
L
V
V
PU
I
=10μA, V
-6
L
OL
IL
PU
CC
≧ 867 [Ω]
PU
PU
≦ I
= 0.9 [V]
= 0.3×3
≧
= 0.4 [V]
OL
is determined by the following factors.
IH
, the larger the consumption current at action.
is determined by the following factors.
○
=0.4V, I
OL
A to be determined by input leak total (I
3-0.4
3×10
IH
IH
=0.7 V
BR24L16/F/FJ/FV/FVT/FVM/FVJ-W
BR24L08/F/FJ/FV/FVT/FVM/FVJ/NUX-W
BR24L04/F/FJ/FV/FVT/FVM/FVJ/NUX-W
OL
-3
=3mA, microcontroller, EEPROM V
CC
∴ R
IL
,
, I
IL
L
) of microcontroller and EEPROM including recommended noise margin 0.1Vcc.
, and V
PU
≦
OLMAX
OL
16/40
-I
V
OL
C
=0.4V and I
I
-V
OL
characteristics of this IC. If R
OL
IH
) of microcontroller and EEPROM including
Microcontroller
OLMAX
L
) of device connected to bus at output of 'H' to
IL
=3mA.
=0.3V
PU
Fig.52 I/O circuit diagram
and SDA should be tR or below.
A0, A1
A0
A0, A1, A2
CC
IL
PU
PU
), select an appropriate value to
is large, action frequency is
R
Bus line
capacity
CBUS
PU
A
Technical Note
2009.09 - Rev.D
IL
BR24LXX
SDA terminal