7008L20JI IDT, 7008L20JI Datasheet

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... BUSY and INT are non-tri-state totem-pole outputs (push-pull). ©2008 Integrated Device Technology, Inc. HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM ◆ IDT7008 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device for BUSY output flag on Master, ◆ M ...

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... High-Speed 64K x 8 Dual-Port Static RAM Description The IDT7008 is a high-speed 64K x 8 Dual-Port Static RAM. The IDT7008 is designed to be used as a stand-alone 512K-bit Dual-Port RAM combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full-speed, error- free operation without the need for additional discrete logic ...

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... All Vcc pins must be connected to power supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. All GND pins must be connected to ground supply. Military, Industrial and Commercial Temperature Ranges (con't.) IDT7008PF (4) PN100-1 100-Pin TQFP (5) Top View 3 6 ...

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... NC NC 10R 12R 15R 11R 14R GND NC 5R 13R IDT7008G (4) G84-3 74 GND 84-PIN PGA (5) TOP VIEW Vcc 5L 13L 11L 14L ...

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... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Truth Table I: Chip Enable < 0.2V >V -0. >V -0. <0.2V NOTES: 1. Chip Enable references are shown above with the actual CE Truth Table II: Non-Contention Read/Write Control (1) Inputs Outputs CE (2) OE SEM ...

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... Ground -65 to +135 Input High Voltage IH -65 to +150 Input Low Voltage NOTES > -1.5V for pulse width less than 10ns. IL 3198 tbl must not exceed Vcc + 10%. TERM Capacitance (T = +25° 1.0mhz) (TQFP Only) A > Vcc + 10%. TERM Symbol C IN (2) C ...

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... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter I Dynamic Operating SEM = V Current (Both Ports Active Standby Current SB1 SEM (Both Ports - TTL Level Inputs Standby Current ...

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... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load Waveform of Read Cycles ADDR ( R/W DATA OUT BUSY OUT Timing of Power-Up Power-Down ( NOTES: 1. Timing depends on which signal is asserted last CE. ...

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... WRITE CYCLE t Write Cycle Time WC (3) t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW (3) t Address Set-up Time AS t Write Pulse Width WP t Write Recovery Time WR t Data Valid to End-of-Write DW (1,2) t Output High-Z Time HZ (5) t Data Hold Time DH (1,2) ...

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... This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2 LOW during R/W controlled write cycle, the write pulse width must be the larger HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as ...

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... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS SEM DATA R/W OE NOTES for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). ...

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... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter BUSY TIMING (M/S BUSY Access Time from Address Match t BAA BUSY Disable Time from Address Not Matched t BDA BUSY Access Time from Chip Enable Low ...

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... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read and BUSY ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins ...

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... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M (1) IH ADDR "A" t APS ADDR " ...

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... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" "A" R/W "A" INT "B" ADDR "B" CE "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. ...

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... NOTES: 1. Pins BUSY and BUSY are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7008 are L R push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address is not met, either BUSY and enable inputs of this port ...

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... BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7008 RAM the BUSY pin is an output if the part is used as a master (M/S pin = V the BUSY pin is an input if the part used as a slave (M/S pin = V in Figure 3 ...

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... The eight semaphore flags reside within the IDT7008 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, CE, and R/W) as they would be used in accessing a standard Static RAM ...

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... Added green indicator to ordering information 10/21/08: Page 19 Removed "IDT" from orderable part number CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc Process/ Temperature Range Blank Commercial (0°C to +70°C) ...