7130SA35J IDT, 7130SA35J Datasheet - Page 18
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7130SA35J
Manufacturer Part Number
7130SA35J
Description
SRAM
Manufacturer
IDT
Series
IDT7130SAr
Type
Asyncronous Static RAMr
Datasheet
1.7130LA55PDGI.pdf
(21 pages)
Specifications of 7130SA35J
Memory Size
8 kbit
Organization
1 K x 8
Access Time
35 ns
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Maximum Operating Current
155 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
PLCC-52
Memory Type
CMOS
Part # Aliases
IDT7130SA35J
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Truth Tables
Truth Table I — Non-Contention Read/Write Control
NOTES:
1. A
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t
4. 'H' = V
Truth Table II — Interrupt Flag
NOTES:
1. Assumes BUSY
2. If BUSY
3. If BUSY
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
Truth Table III — Address BUSY
Arbitration
NOTES:
1. Pins BUSY
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs
3. Writes to the left port are internally ignored when BUSY
CE
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
X
X
H
L
R/W
IDT7140 (slave). BUSY
outputs. On slaves the BUSY
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If t
result. BUSY
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSY
the pin.
R/W
L
0L
X
X
H
H
X
X
X
L
L
– A
L
IH
CE
10L
L
R
, 'L' = V
X
X
H
L
= V
= V
R
Inputs
L
≠ A
and BUSY
L
IL
IL
CE
CE
, then No Change.
and BUSY
, then No Change.
H
H
L
L
L
0R
X
X
IL
L
L
L
NO MATCH
L
, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
= BUSY
– A
A
A
MATCH
MATCH
MATCH
0R
0L
R
Inputs
10R
outputs are driving LOW regardless of actual logic level on
-A
-A
R
X
are both outputs for IDT7130 (master). Both are inputs for
9L
9R
R
.
outputs on the IDT7130 are open drain, not push-pull
Left Port
R
outputs can not be LOW simultaneously.
OE
(1)
OE
X
X
X
H
X
X
X
= V
APS
L
L
X
L
input internally inhibits writes.
IH
is not met, either BUSY
BUSY
(2)
H
H
H
DATA
A
WDD
L
DATA
9L
Outputs
3FF
3FE
(1)
D
X
X
-A
Z
Z
Z
0-7
and t
0L
OUT
IN
BUSY
DDD
(2)
H
H
H
Port Disabled and in Power-Down Mode, I
Data on Port Written into Memory
Data in Memory Output on Port
High Impedance Outputs
timing.
L
CE
R
outputs are driving LOW
(1)
INT
L
X
X
H
R
L
or BUSY
(3)
(2)
L
= CE
Write Inhibit
Function
L
Normal
Normal
Normal
R
= V
= LOW will
(1,4)
R/W
X
X
L
X
2689 tbl 15
IH
, Power-Down Mode, I
R
(3)
18
CE
X
X
L
L
R
(3)
Military, Industrial and Commercial Temperature Ranges
(2)
Right Port
OE
X
L
X
X
SB1
R
SB2
or I
or I
Function
SB3
SB4
A
9R
3FF
3FE
X
X
-A
0R
(4)
INT
H
X
X
L
(2)
(3)
R
Set Right INT
Reset Right INT
Set Left INT
Reset Left INT
Function
L
R
Flag
L
Flag
R
Flag
Flag
2689 tbl 13
2689 tbl 14