7130SA35J IDT, 7130SA35J Datasheet - Page 14
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7130SA35J
Manufacturer Part Number
7130SA35J
Description
SRAM
Manufacturer
IDT
Series
IDT7130SAr
Type
Asyncronous Static RAMr
Datasheet
1.7130LA55PDGI.pdf
(21 pages)
Specifications of 7130SA35J
Memory Size
8 kbit
Organization
1 K x 8
Access Time
35 ns
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Maximum Operating Current
155 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
PLCC-52
Memory Type
CMOS
Part # Aliases
IDT7130SA35J
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
NOTES:
1.
2.
3.
4.
5.
6.
7.
BUSY TIMING (For MASTER IDT 7130)
t
t
t
t
t
t
t
t
t
BUSY INPUT TIMING (For SLAVE IDT 7140)
t
t
t
t
BUSY TIMING (For MASTER IDT 7130)
t
t
t
t
t
t
t
t
t
BUSY INPUT TIMING (For SLAVE IDT 7140)
t
t
t
t
BAA
BDA
BAC
BDC
WH
WDD
DDD
APS
BDD
WB
WH
WDD
DDD
BAA
BDA
BAC
BDC
WH
WDD
DDD
APS
BDD
WB
WH
WDD
DDD
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Symbol
Symbol
PLCC, TQFP and STQFP packages only.
Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY."
To ensure that the earlier of the two ports wins.
t
To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.
To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
'X' in part numbers indicates power rating (S or L).
BDD
is a calculated parameter and is the greater of 0, t
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Hold After BUSY
Write Pulse to Data Delay
Write Data Valid to Read Data Delay
Arbitration Priority Set-up Time
BUSY Disable to Valid Data
Write to BUSY Input
Write Hold After BUSY
Write Pulse to Data Delay
Write Data Valid to Read Data Delay
BUSY Access Time from Address]
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Hold After BUSY
Write Pulse to Data Delay
Write Data Valid to Read Data Delay
Arbitration Priority Set-up Time
BUSY Disable to Valid Data
Write to BUSY Input
Write Hold After BUSY
Write Pulse to Data Delay
Write Data Valid to Read Data Delay
(5)
(5)
(6)
(6)
(6)
(6)
(2)
(2)
(2)
(2)
(4)
(4)
(3)
(3)
Parameter
(2)
(2)
(2)
(2)
WDD
Parameter
– t
WP
(actual) or t
DDD
– t
14
DW
(actual).
Military, Industrial and Commercial Temperature Ranges
Min.
____
____
____
____
____
____
____
____
____
12
12
5
0
Com'l Only
7130X20
7140X20
Max.
(1)
(1)
____
____
____
____
20
20
20
20
40
30
25
40
30
(7)
Min.
Min.
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
15
15
20
20
5
0
5
0
Com'l, Ind
& Military
Com'l, Ind
& Military
7130X25
7140X25
7130X55
7140X55
Max.
Max.
____
____
____
____
20
20
20
20
50
35
35
50
35
____
____
____
____
30
30
30
30
80
55
55
80
55
Min.
Min.
____
____
____
____
____
____
____
____
____
20
20
____
____
____
____
____
____
____
____
____
20
20
5
0
5
0
Com'l, Ind
& Military
& Military
7130X100
7140X100
7130X35
7140X35
Com'l
Max.
Max.
____
____
____
____
120
100
120
100
20
20
20
20
60
35
35
60
35
____
____
____
____
50
50
50
50
65
2689 tbl 11a
2689 tbl 11b
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns